Integrated Circuit Having a Cell with a Resistivity Changing Layer

• US 20090039329A1
• Filed: 08/10/2007
• Published: 02/12/2009
• Est. Priority Date: 08/10/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Willer, Josef, Hofmann, Franz
• Granted Patent: US 7,772,580 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/041 Modification of the switching material, e.g. post-treatment, doping
• CPC Class Codes: H10N 70/046 by diffusion, e.g. photo-dissolution
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/253 having three or more terminals, e.g. transistor-like devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 : Other compounds of groups 13-15, e.g. elemental or compound semiconductors
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.

Claims

1. An integrated circuit comprising:

a first source/drain region;

a second source/drain region;

an active region between the first source/drain region and the second source/drain region;

a gate stack disposed above the active region; and

a resistivity changing layer structure disposed above the gate stack, wherein the resistivity changing layer structure comprises a resistivity changing layer, wherein the resistivity changing layer comprises a resistivity changing material.

2. The integrated circuit of claim 1, wherein the first and second source/drain regions are source/drain regions of a memory cell.

3. The integrated circuit of claim 1, further comprising an electrically conductive connecting structure next to the gate stack to electrically connect the resistivity changing layer with the first source/drain region or the second source/drain region.

4. The integrated circuit of claim 3, wherein the electrically conductive connecting structure comprises at least one electrically conductive spacer disposed next to the gate stack.

5. The integrated circuit of claim 3, wherein the electrically conductive connecting structure comprises a material formed using a vapor deposition process.

6. The integrated circuit of claim 3, wherein the electrically conductive connecting structure comprises polysilicon or tungsten silicide.

7. The integrated circuit of claim 3, wherein the gate stack comprises a plurality of layers being arranged above one another.

8. The integrated circuit of claim 7, wherein the gate stack comprises:

a first insulating layer disposed above the active region;

an electrically conductive gate region disposed above the first insulating layer; and

a second insulating layer disposed above the electrically conductive gate region.

9. The integrated circuit of claim 1, further comprising an electrode layer disposed above the gate stack, wherein the resistivity changing layer is disposed above the electrode layer.

10. An integrated circuit comprising:

a field effect transistor structure which comprises a gate stack; and

a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure comprises a resistivity changing material which is configured to change its resistivity in response to an application of an electrical voltage to the resistivity changing material structure.

11. The integrated circuit of claim 10, wherein the field effect transistor structure comprises a part of a memory cell.

12. The integrated circuit of claim 10, further comprising an electrically conductive connecting structure next to the gate stack to electrically connect a resistivity changing layer with a source/drain region of the field effect transistor structure.

13. The integrated circuit of claim 12, wherein the electrically conductive connecting structure comprises at least one electrically conductive spacer disposed next to the gate stack.

14. The integrated circuit of claim 12, wherein the electrically conductive connecting structure comprises a material formed using a vapor deposition process.

15. The integrated circuit of claim 12, wherein the electrically conductive connecting structure comprises polysilicon or tungsten silicide.

16. The integrated circuit of claim 12, wherein the gate stack comprises a plurality of layers arranged above one another.

17. The integrated circuit of claim 16, wherein the gate stack comprises

a first insulating layer disposed above an active region;

an electrically conductive gate region disposed above the first insulating layer; and

a second insulating layer disposed above the electrically conductive gate region.

18. The integrated circuit of claim 10, further comprising an electrode layer disposed above the gate stack, wherein the resistivity changing layer is disposed above the electrode layer.

19. A method for manufacturing an integrated circuit, the method comprising:

forming a first source/drain region;

forming a second source/drain region;

forming an active region between the first source/drain region and the second source/drain region;

forming a gate stack on or above the active region; and

forming a resistivity changing layer on or above the gate stack, wherein the resistivity changing layer comprises a resistivity changing material.

20. The method of claim 19, wherein forming the first and second source/drain region comprises forming source/drain regions of a memory cell.

21. The method of claim 19, further comprising forming an electrically conductive connecting structure next to the gate stack to electrically connect the resistivity changing layer with the first source/drain region or the second source/drain region.

22. The method of claim 21, wherein forming the electrically conductive connecting structure comprises forming at least one electrically conductive spacer next to the gate stack.

23. The method of claim 21, wherein forming the electrically conductive connecting structure is carried out using a vapor deposition process.

24. The method of claim 21, wherein the electrically conductive connecting structure comprises polysilicon or tungsten silicide.

25. The method of claim 21, wherein forming the gate stack comprises forming a plurality of layers on or above one another.

26. The method of claim 25, wherein forming the gate stack comprises:

forming a first insulating layer on or above the active region;

forming an electrically conductive gate region on or above the first insulating layer; and

forming a second insulating layer on or above the electrically conductive gate region.

27. The method of claim 19, further comprising:

forming an electrode layer on or above the gate stack; and

forming the resistivity changing layer on or above the electrode layer.

28. A method for manufacturing an integrated circuit, the method comprising:

forming a field effect transistor structure which includes a gate stack; and

forming a resistivity changing material structure over the gate stack, wherein the resistivity changing material structure comprises a resistivity changing material that is configured to change its resistivity in response to an application of an electrical voltage to the resistivity changing material structure.

29. The method of claim 28, wherein forming a field effect transistor structure comprises forming part of a memory cell.

30. The method of claim 28, further comprising, forming an electrically conductive connecting structure next to the gate stack to electrically connect a resistivity changing layer with a source/drain region of the field effect transistor structure.

31. The method of claim 30, wherein forming the electrically conductive connecting structure comprises forming at least one electrically conductive spacer next to the gate stack.

32. The method of claim 30, wherein forming the electrically conductive connecting structure comprises performing a vapor deposition process.

33. The method of claim 30, wherein the electrically conductive connecting structure comprises polysilicon or tungsten silicide.

34. The method of claim 30, wherein forming the gate stack comprises forming a plurality of layers on or above one another.

35. The method of claim 30, wherein forming the gate stack comprises:

forming a first insulating layer on or above the active region;

forming an electrically conductive gate region on or above the first insulating layer; and

forming a second insulating layer on or above the electrically conductive gate region.

36. The method of claim 30, further comprising:

forming an electrode layer on or above the gate stack; and

forming the resistivity changing layer on or above the electrode layer.

37. A memory module, comprising:

a plurality of integrated circuits, wherein at least one integrated circuit of the plurality of integrated circuits comprises a cell, the cell comprising;

a first source/drain region;

a second source/drain region;

an active region between the first source/drain region and the second source/drain region;

a gate stack disposed above the active region; and

a resistivity changing layer structure disposed above the gate stack, wherein the resistivity changing layer structure comprises a resistivity changing layer, wherein the resistivity changing layer comprises a resistivity changing material.

38. The memory module of claim 37, wherein the memory module is a stackable memory module in which at least some of the integrated circuits are stacked one above the other.