LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR DEVICE FABRICATION

• US 20090039361A1
• Filed: 07/25/2008
• Published: 02/12/2009
• Est. Priority Date: 05/17/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Li, Jizhong, Lochtefeld, Anthony J.
• Granted Patent: US 9,153,645 B2
• Time in Patent Office: Days
• US Class Current: 257/94
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 31/036 characterised by their crystalline structure or particular orientation of the crystalline planes
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/18 : within the light emitting region
• CPC Class Codes: H01S 5/22 : having a ridge or stripe structure
• CPC Class Codes: H01S 5/323 : in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
• CPC Class Codes: Y02E 10/544 : Solar cells from Group III-V materials

Abstract

A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.

Claims

1. A method of forming a structure, the method comprising:

providing a dielectric sidewall, proximate a substrate, with a height h, the substrate comprising a first crystalline semiconductor material and a top surface having a first crystal orientation, the dielectric sidewall defining an opening with a width w exposing a portion of the substrate;

defining, in the exposed portion of the substrate, a recess with a maximum depth d and a recessed surface comprising a second crystal orientation; and

forming, in the recess, a second crystalline semiconductor material having a lattice mismatch with the first crystalline semiconductor material, the lattice mismatch creating defects in the second crystalline semiconductor material, the defects terminating at a distance H above a deepest point of the recess.

2. The method of claim 1, wherein H is less than or equal to h+d.

3. The method of claim 2, wherein H is less than or equal to d.

4. The method of claim 1, wherein H is less than or equal to w.

5. The method of claim 1, wherein a ratio of h+d to w is greater than or equal to one.

6. The method of claim 1, wherein the recess has a v-shaped profile.

7. The method of claim 1, wherein the first crystal orientation is (100), and the second crystal orientation is not (100).

8. The method of claim 7, wherein the second crystal orientation is (111).

9. The method of claim 1, further comprising forming a third crystalline semiconductor material above the second crystalline semiconductor material.

10. The method of claim 9, wherein the third crystalline material is lattice mismatched to the second crystalline material, and the lattice mismatch between the second crystalline semiconductor material and the first crystalline semiconductor material is less than a lattice mismatch between the third crystalline semiconductor material and the first crystalline semiconductor material.

11. The method of claim 9, wherein a boundary defined by the interface between the second and third crystalline semiconductor materials is proximate a boundary defined by the interface between the exposed portion of the substrate and the dielectric sidewall.

12. The method of claim 1, further comprising removing the substrate to expose a bottom portion of the second crystalline semiconductor material.

13. The method of claim 12, wherein the exposed bottom portion of the second crystalline semiconductor material comprises a non-planar surface.

14. The method of claim 12, further comprising, after removing the substrate, removing at least part of the bottom portion of the second crystalline semiconductor material.

15. The method of claim 14, wherein removing at least part of the bottom portion of the second crystalline semiconductor material comprises removing a majority of the defects.

16. The method of claim 1, further comprising forming a photonic structure disposed at least partially above the second crystalline semiconductor material.

17. The method of claim 16, wherein the photonic structure comprises at least one of an LED, a PV cell, or a laser diode.

18. The method of claim 1, further comprising forming a photonic structure disposed at least partially inside the opening.

19. A semiconductor structure comprising:

a substrate comprising a first crystalline semiconductor material having a top surface with a first crystal orientation, the substrate including a recess therein with a maximum depth d, the recess comprising a recessed surface with a second crystal orientation;

a dielectric sidewall of height h disposed proximate the recess; and

a second crystalline semiconductor material of maximum width w disposed in the recess, the recess defining an interface between the second crystalline semiconductor material and the substrate,

wherein the second crystalline semiconductor material has a lattice mismatch with the first crystalline semiconductor material, the lattice mismatch creates defects in the second crystalline semiconductor material, and the defects terminate at a distance H above a bottom surface of the recess.

20. The structure of claim 19, wherein H is less than h+d.

21. The structure of claim 20, wherein H is less than d.

22. The structure of claim 19, wherein H is less than or equal to w.

23. The structure of claim 19, wherein a ratio of h+d to w is greater than or equal to one.

24. The structure of claim 19, wherein the recess has a v-shaped profile.

25. The structure of claim 19, wherein the first crystal orientation is (100), and the second crystal orientation is not (100).

26. The structure of claim 25, wherein the second crystal orientation is (111).

27. The structure of claim 19, further comprising a third crystalline semiconductor material disposed above the second crystalline semiconductor material.

28. The structure of claim 27, wherein the third crystalline material is lattice mismatched to the second crystalline material, and the lattice mismatch between the second crystalline semiconductor material and the first crystalline semiconductor material is less than a lattice mismatch between the third crystalline semiconductor material and the first crystalline semiconductor material.

29. The structure of claim 27, wherein a boundary defined by the interface between the second and third crystalline semiconductor materials is proximate a boundary defined by the interface between the exposed portion of the substrate and the dielectric sidewall.

30. The structure of claim 19, further comprising a photonic structure disposed at least partially above the second crystalline semiconductor material.

31. The structure of claim 30, wherein the photonic structure comprises at least one of an LED, a PV cell, or a laser diode.

32. The structure of claim 19, further comprising a photonic structure disposed at least partially inside the opening.

33. The structure of claim 19, further comprising a third crystalline semiconductor material disposed over the second crystalline semiconductor material, wherein a bandgap of the third crystalline semiconductor material is lower than a bandgap of the second crystalline semiconductor material.

34. The structure of claim 19, further comprising a third crystalline semiconductor material disposed over the second crystalline semiconductor material, wherein the second crystalline semiconductor material is n-doped and the third crystalline semiconductor material is p-doped.

35. The structure of claim 19, further comprising a third crystalline semiconductor material disposed over the second crystalline semiconductor material, wherein the second crystalline semiconductor material is GaAs and the third crystalline semiconductor material is InP.

36. A semiconductor structure comprising:

a photonic structure; and

a crystalline semiconductor disposed above the photonic structure,

wherein a surface of the crystalline semiconductor comprises a plurality of ridges, a width of one ridge in the plurality of ridges is less than or equal to a visible light wavelength, and a spacing of the plurality of ridges is less than or equal to the visible light wavelength.

37. The structure of claim 36, wherein the photonic structure comprises at least one of an LED, a PV cell, or a laser diode.

38. The structure of claim 36, further comprising a metal contact disposed above the crystalline semiconductor.

39. The structure of claim 38, wherein the metal contact conforms to at least one ridge.

40. A method of forming a structure, the method comprising:

defining a recess with a maximum depth d in a top surface of a (100) substrate comprising a first crystalline semiconductor material, the recess exposing a (111) surface of the substrate; and

forming a III-nitride material in the recess, wherein the III-nitride has a lattice mismatch with the first crystalline semiconductor material and the lattice mismatch creates defects in the III-nitride material perpendicular to the (111) surface, resulting in a substantially defect-free region in the III-nitride material.