Vertically integrated flash EPROM for greater density and lower cost

• US 20090039407A1
• Filed: 04/24/2008
• Published: 02/12/2009
• Est. Priority Date: 03/17/2005
• Status: Abandoned Application

• Current Assignee: Madhukar B. Vora
• Original Assignee: Madhukar B. Vora
• Inventors: Vora, Madhukar B.
• Application Number:
  US12/150,079
• Publication Number:
  US 20090039407A1
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolative memory in the form of a vertical flash EPROM with high density and low cost. A vertical MOS transistor is formed in well etched into a semiconductor substrate, the substrate having source, body and drain regions formed by ion implantation. A thin gate oxide or oxide-nitride-oxide (ONO) layer is formed in the well and a self-aligned floating gate of polysilicon is formed over the gate oxide in the well to overlie the body region. An anisotropic etch is used to form the self aligned floating gate so as to remove all horizontal components and leave no portion of said floating gate extending beyond the perimeter of said well such that its lateral extents are determined by the anisotropic etch and not photolithography. L_eff is determined by the energy of the implants used for form the source and drain regions and not by lithography. A deep field oxide bounding parts of said well keeps the coupling ratio good at all feature sizes. A vertically oriented NMOS and PMOS transistor are also disclosed.

Claims

1. (canceled)

2. (canceled)

3. (canceled)

4. (canceled)

5. A process for forming a vertically oriented EPROM cell comprising steps of:

using ion implants to dope source and drain regions in a substrate doped to the desired conductivity of a body region of a vertically oriented EPROM cell and controlling the implant energy of said ion implants to establish a desired gate length for a body region in said substrate between said source and drain regions;

forming a recess in said substrate deep enough to penetrate at least partially into said source region;

forming a gate insulator layer on the walls of said recess and an insulation layer on the bottom of said recess;

depositing a floating gate material in said recess and using an anisotropic etch to etch away horizontal components of said floating gate material to leave a self-aligned floating gate which does not extend laterally beyond a perimeter of said recess;

forming a control gate over and insulated from said floating gate and a word line in contact with said control gate; and

forming a bit line in contact with said drain region.

6. The process of claim 5 further comprising the step of forming deep field oxide regions bordering at least some of the walls of said recess and extending down into said substrate far enough to reduce a capacitance of a capacitor C1 sufficiently to obtain a desired coupling ratio regardless of feature size, where C1 is the capacitance between floating gate and said body region of said substrate.

7. (canceled)

8. A process for forming a vertically oriented n-MOS transistor comprising steps of:

using ion implants to dope source and drain regions in a substrate doped to the desired conductivity of a body region of a vertically oriented n-MOS transistor and controlling the implant energy of said ion implants to establish a desired gate length for a body region in said substrate between said source and drain regions;

forming a recess in said substrate deep enough to penetrate at least partially into said source region;

forming a gate insulator layer on the walls of said recess and an insulation layer on the bottom of said recess;

depositing a conductive gate material in said recess and using an anisotropic etch to etch away horizontal components of said gate material to leave a self-aligned gate which does not extend laterally beyond a perimeter of said recess;

forming a conductive paths to said gate and said source and drain regions.

9. (canceled)

10. (canceled)

11. (canceled)

12. A process for forming a recessed gate window for a vertically oriented EPROM cell in a semiconductor substrate so as to substantially improve the coupling ratio as feature sizes are reduced by reducing the capacitance C1 between a floating gate and a doped region of a semiconductor substrate forming the body of a vertically oriented EPROM cell and through which a conductive channel is selectively formed, said process comprising:

forming trenches in a doped semiconductor substrate so as to border a predetermined part of the perimeter of an area where a recessed gate window will be formed said trenches being deep enough to exceed the depth of a recessed gate window to be formed later;

doing an angled implant of impurities of a predetermined conductivity type so as to implant impurities into the walls and bottom of said trenches;

depositing CVD oxide in said trenches to form deep field oxide structures; and

forming said recessed gate window so as to border said trenches.

13. The process of claim 12 wherein said recessed gate window has four sides, and said trenches are formed so as to border two of said four sides.

14. A process for forming a recessed gate window for a vertically oriented EPROM cell in a semiconductor substrate so as to substantially improve the coupling ratio as feature sizes are reduced by reducing the capacitance C1 between a floating gate and a doped region of a semiconductor substrate forming the body of a vertically oriented EPROM cell and through which a conductive channel is selectively formed, said process comprising:

forming trenches in a doped semiconductor substrate so as to border part of the perimeter of an area where a recessed gate window will be formed said trenches being deep enough to exceed the depth of a recessed gate window to be formed later;

depositing boron doped CVD oxide in said trenches to form deep field oxide structures; and

forming said recessed gate window so as to border said trenches.

15. The process of claim 14 wherein said recessed gate window has four sides, and said trenches are formed so as to border two of said four sides.

16. A vertically oriented EPROM cell comprising:

a semiconductor substrate having a vertical trench formed therein;

means for forming a vertically oriented EPROM cell in said vertical trench with at least one self aligned floating gate in each said vertical trench and a control gate and a bit line and a word line;

means for causing a coupling ratio of said vertically oriented EPROM cell to remain high enough as feature sizes are scaled down to allow effective programming voltages to be used which are small enough to not cause damage by punchthrough.

23. The apparatus of claim 16 or 19 wherein said floating gate is comprised of composite silicon dioxide and silicon nitride to form an MNOS EPROM device.

17. (canceled)

18. (canceled)

19. A pair of vertically oriented EPROM memory cells formed in the same recessed gate window formed in a substrate, comprising:

a semiconductor substrate having formed therein a first layer doped with an impurity so as to have a first conductivity type such as P type and so as to act as the body of a vertically oriented EPROM cell through which a conductive channel region will be formed under predetermined conditions of stored charge and applied voltage, and having formed therein two separate second layers each of which is doped with an impurity so as to have a second conductivity type such as N type and adjacent to said first layer and electrically insulated from each other so as to act as separate drains of two separate vertically oriented EPROM cells to be formed in a recess in said substrate;

and wherein said recess is formed in said semiconductor substrate so as to penetrate down through said second and first layers, said recess having a circumference;

a field oxide layer formed so as to bound at least enough of said circumference of said recess so as to cause a coupling ratio to remain high enough as feature sizes of said vertically oriented EPROM cell are scaled downward in size to allow programming voltages to be used which are low enough to not cause punch through;

an insulating layer formed on a bottom of said recess;

an area of said substrate beneath said insulating layer formed on said bottom of said recess which has been doped to said conductivity type so as to act as a source for said vertically oriented EPROM transistor;

a gate insulating layer formed so as to cover at least part of the inside surface of said recess;

a pair of floating gates formed on top of said gate insulating layer and insulated from each other and formed at least at locations of said gate insulating layer which are in contact with said first and second layers in said substrate as opposed to portions of said gate insulating layer which are in contact with said field oxide;

a control gate formed in said recess and having a conductive portion which extends to make electrical contact with control gates of other EPROM cells in a row of said array so as to act as a word line; and

an insulating material insulating said control gate from said floating gate;

and wherein said recess walls are covered by said gate insulating layer and wherein said floating gate covers all said gate insulating layer but is split into two halves which are insulated from each other by an insulating layer.

20. A pair of vertically oriented EPROM memory cells formed in the same recess in a substrate, comprising:

a semiconductor substrate doped to a conductivity desired for the body of a vertically oriented EPROM cell;

a source and a pair of separate drain regions formed in said substrate by ion implants with the energy of said ion implants and not photolithography determining the effective gate length of the vertically oriented EPROM cell by determining the distance between the source and drain regions, each area in said substrate between said source and each of said separate drain regions being referred to herein as a body region;

a recess formed down into said substrate so as to penetrate at least partially into said source region, said recess having a perimeter;

deep field oxide bounding at least some portions of said perimeter of said recess and extending deep enough into said substrate at the portions of said recess which are bounded by said deep field oxide so as to decrease the value of a capacitance C1 between floating gates to be formed in said recess and said semiconductor substrate;

a gate insulator formed on walls of said recess and an insulation layer on the bottom of said recess, said source region being part of a doped area formed by ion implantation below said insulation layer formed on said bottom of said recess and forming a buried first bit line shared by a pair of vertically oriented EPROM memory cells to be formed in said recess;

a pair of self-aligned floating gates, each formed on at least a portion of said gate insulator so as to overlie a said body region, said self-aligned floating gates each having lateral extents beyond a perimeter of said recess which are determined by the inherent characteristics of an anisotropic etch used to form said self-aligned floating gate and not by photolithography;

a conductive control gate formed between said self aligned floating gates and insulated therefrom;

means for forming a word line in electrical contact with said control gate; and

means for forming a second bit lines in electrical contact with each of said separate drain regions.

21. A vertically oriented MOS transistor, comprising:

a semiconductor substrate doped to a conductivity desired for the body of a vertically oriented MOS transistor;

a source and drain region formed in said substrate by ion implants with the energy of said ion implants and not photolithography determining the effective gate length of the vertically oriented MOS transistor by determining the distance between the source and drain regios, each area in said substrate between said source and said drain region being referred to herein as a body region;

a recess formed down into said substrate so as to penetrate at least partially into said source region, said recess having a perimeter;

a gate insulator formed on walls of said recess and an insulation layer covering at least a portion of a bottom surface of said recess, said source region being part of a doped area formed by ion implantation below said insulation layer formed on said bottom of said recess;

a conductive gate formed over said gate insulator and positioned such that a predetermined voltage applied to said conductive gate will form a conductive channel through said body region between said source and drain regions;

means for forming an electrical contact to said gate;

means for forming an electrical contact to said source region; and

means for forming an electrical contact with said drain region.

22. A nonvolatile memory cell comprising:

a semiconductor substrate;

a vertical MOS transistor formed by alternating N-type and P-type doped layers in said substrate intersecting a well etched into said substrate so as to form a source and drain regions separated by a body region, said well having a gate of conductive material formed therein and insulated from said alternating N-type and P-type materials by a layer of gate insulating material and overlying said body region;

a contact comprising a layer of conductive material formed on said substrate so as to extend down into said well and make contact with said gate; and

means for making electrical contact with said source and drain regions.