Negative Differential Resistance Pull Up Element For DRAM

• US 20090039438A1
• Filed: 10/13/2008
• Published: 02/12/2009
• Est. Priority Date: 12/21/2001
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Liu, Tsu-Jae King
• Granted Patent: US 7,995,380 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.

Claims

1. A method of operating a random access memory (RAM) cell, the method comprising:

coupling a pull-up element with a switchable current path between a storage node of the RAM cell and a high voltage potential source;

maintaining the switchable current path of the pull-up element in an off condition during a first period when the RAM cell is storing a first value at the storage node; and

turning on the switchable current path of the pull-up element during at least portions of a second period when the RAM cell is storing a second value at the storage node to refresh the second value at the storage node.

2. The method of claim 1, wherein the pull-up element is a negative differential resistance (NDR) device.

3. The method of claim 2, wherein the NDR device is a metal insulator semiconductor field effect transistor (MISFET) that includes a trapping layer for trapping electrons from the switchable current path.

4. The method of claim 3, wherein maintaining the switchable current path of the pull-up element in the off condition during the first period and turning on the switchable current patch of the pull-up element during at least portions of the second period comprises supplying a gate bias signal to a gate of the NDR device, the gate bias signal comprising periodic high voltage pulses, wherein the periodic high voltage pulses are greater than a threshold voltage of the NDR device.

5. A method of operating a random access memory (RAM) comprising a plurality of memory cells,

wherein each of the plurality of memory cells comprises a pull-up device and a storage capacitor connected in series between a high voltage source and a low voltage source, and

wherein a junction between the pull-up device and the storage capacitor form a data storage node,

the method comprising applying high bias voltage pulses to the gate of the pull-up device in each of the plurality of memory cells,

wherein when a first voltage potential is stored at the data storage node, each high bias voltage pulse causes the pull-up device to be placed in an ON state, and

wherein when a second voltage potential is stored at the data storage node, the high bias voltage pulses do not cause the pull-up device to be placed in an ON state.