CIRCUIT MEMBER, MANUFACTURING METHOD FOR CIRCUIT MEMBERS, SEMICONDUCTOR DEVICE, AND SURFACE LAMINATION STRUCTURE FOR CIRCUIT MEMBER

• US 20090039486A1
• Filed: 04/26/2006
• Published: 02/12/2009
• Est. Priority Date: 04/26/2005
• Status: Active Grant

• Current Assignee: Dai Nippon Printing Company Limited
• Original Assignee: Dai Nippon Printing Company Limited
• Inventors: Saito, Hiroyuki, Shimazaki, Yo, Masuda, Masachika, Matsumura, Kenji, Fukuchi, Masaru, Ikezawa, Takao
• Granted Patent: US 8,742,554 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/85464 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Claims

1. A circuit member including a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, comprising:

rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion; and

smooth surfaces formed on downsides of the die pad portion and the lead portion, wherein

the die pad portion and the lead portion are configured to be buried in a sealing resin, having a downside of the lead portion exposed.

2. The circuit member as claimed in claim 1, comprising metallic skins formed on obverse surfaces of the die pad portion and the lead portion, for enhancement of connectability with a bonding wire and a solder paste.

11. The circuit member as claimed in claim 1, wherein a rough surface is treated by a micro-etching solution having hydrogen peroxide and sulfuric acid as components.

3. A circuit member including a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, comprising:

smooth surfaces formed on a portion of an upside of the die pad portion and on a portion of an upside of the lead portion to be connected to a bonding wire;

metallic skins on the smooth surfaces; and

rough surfaces formed on regions excepting downsides of the die pad portion and the lead portion and regions where the metallic skins are formed.

4. The circuit member as claimed in claim 3, wherein a metallic skin comprises an Ag skin.

5. The circuit member as claimed in claim 3, wherein a metallic skin comprises a Ni skin and a Pd skin laminated in order on the rolled copper plate.

6. The circuit member as claimed in claim 3, wherein a metallic skin comprises a Ni skin, a Pd skin, and an Au skin laminated in order on the rolled copper plate.

7. The circuit member as claimed in claim 3, wherein a rough surface has a surface roughness (Ra) of 0.3 μ

m or more.

8. The circuit member as claimed in claim 4, wherein the Ag skin has a thickness within a range of 2 to 15 μ

m.

9. The circuit member as claimed in claim 5, wherein the Ni skin has a thickness within a range of 0.5 to 2 μ

m, and the Pd skin has a thickness within a range of 0.005 to 0.2 μ

m.

10. The circuit member as claimed in claim 6, wherein the Ni skin has a thickness within a range of 0.5 to 2 μ

m, the Pd skin has a thickness within a range of 0.005 to 0.2 μ

m, and the Au skin has a thickness within a range of 0.003 to 0.01 μ

m.

12. A manufacturing method for circuit members, comprising:

forming a frame substrate with a die pad portion and a lead portion, by patterning a rolled copper plate or a rolled copper alloy plate;

roughing upside surfaces and lateral wall surfaces of the frame substrate, using a micro-etching solution having hydrogen peroxide and sulfuric acid as components, with a making material covering downside surfaces of the frame substrate; and

having, past a removal of the masking material, metallic skins laminated on obverse surfaces of the frame substrate.

14. The manufacturing method for circuit members as claimed in claim 12, wherein the step of laminating the metallic skins comprises laminating an Ag skin on an obverse surface of the frame substrate.

15. The manufacturing method for circuit members as claimed in claim 12, wherein the step of laminating the metallic skins comprises laminating a Ni skin and a Pd skin in order on an obverse surface of the frame substrate.

16. The manufacturing method for circuit members as claimed in claim 15, comprising laminating an Au skin on the Pd skin.

13. A manufacturing method for circuit members, comprising:

forming a frame substrate with a die pad portion and a lead portion, by patterning a rolled copper plate or a rolled copper alloy plate;

laminating metallic skins on an upside surface of the die pad portion, and on a portion of the lead portion to be connected to a bonding wire;

surface-roughing the frame substrate, using a micro-etching solution having hydrogen peroxide and sulfuric acid as principal components, with a masking material covering downside surfaces of the frame substrate having the metallic skins laminated thereon; and

removing the masking material.

17. A semiconductor device comprising:

a circuit member composed of a rolled copper plate or a rolled copper alloy plate, comprising;

a die pad portion and a lead portion;

rough surfaces formed on upsides and lateral wall sides of the die pad portion and the lead portion;

smooth surfaces formed on downsides of the die pad portion and the lead portion; and

metallic skins on the surfaces;

a semiconductor chip mounted on an upside of the die pad portion;

a bonding wire interconnecting the semiconductor chip and the lead portion; and

an electrically insulating sealing resin configured to have the circuit member, the semiconductor chip, and the bonding wire sealed in, with a downside of the lead portion exposed.

18. A semiconductor device comprising:

a circuit member composed of a rolled copper plate or a rolled copper alloy plate, comprising;

a die pad portion and a lead portion;

smooth surfaces formed on an upside of the die pad portion, and on a portion of an obverse side of the lead portion to be connected to a bonding wire;

metallic skins on the smooth surfaces; and

rough surfaces formed on regions excepting reverse sides of the die pad portion and the lead portion and regions where the metallic skins are formed;

a semiconductor chip mounted on the upside of the die pad portion;

the bonding wire interconnecting the semiconductor chip and the lead portion; and

an electrically insulating sealing resin configured to have the circuit member, the semiconductor chip, and the bonding wire sealed in, with a downside of the lead portion exposed.

19. A surface lamination structure for a circuit member to be joined to an insulating resin, comprising:

a rough surface formed on an obverse side of a conductive substrate composed of a rolled copper plate or a rolled copper alloy, with a surface roughness (Ra) of 0.3 μ

m or more; and

a Ni skin and a Pd skin laminated in order on the rough surface, wherein

the Ni skin has a thickness within a range of 0.5 to 2 μ

m, and the Pd skin has a thickness within a range of 0.005 to 0.2 μ

m.

20. The surface lamination structure for a circuit member as claimed in claim 19, further comprising an Au skin laminated on the Pd skin, with a thickness within a range of 0.003 to 0.01 μ

m.