STACKED MEMORY DEVICE

• US 20090039492A1
• Filed: 05/20/2008
• Published: 02/12/2009
• Est. Priority Date: 08/06/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KANG, Uk-song, CHUNG, Hoe-ju, LEE, Jung-bae
• Granted Patent: US 7,999,367 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA

Abstract

A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

Claims

1. A semiconductor memory device comprising:

a buffer chip comprising a plurality of base bond pads receiving externally provided write data and providing read data;

a first memory chip comprising first bond pads and seated in a central portion of a first interposer chip, the first interposer chip being larger in area than the first memory chip and comprising second bond pads respectively connecting the first bond pads of the first memory chip, and a plurality of through silicon vias (TSVs) formed proximate at least one edge of the first interposer chip;

a second memory chip comprising first bond pads and seated in a central portion of a second interposer chip, the second interposer chip being larger in area than the second memory chip and comprising second bond pads respectively connecting the first bond pads of the second memory chip, and a plurality of TSVs formed proximate at least one edge of the second interposer chip and respectively connected via vertical connection elements to the plurality of TSVs in the first interposer chip,

wherein the first interposer is stacked on the second interposer and the plurality of TSVs in the second interposer chip are respectively connected to the plurality of base bond pads.

2. The device of claim 1, wherein the first interposer chip further comprises a plurality of distribution lines respectively connecting a second bond pad with at least one of the plurality of TSVs.

3. The device of claim 1, wherein the first memory chip is a bare semiconductor die or packaged semiconductor die.

4. The device of claim 1, wherein the first memory chip is a memory core chip.

5. The device of claim 1, wherein the buffer chip further comprises:

a plurality of base TSVs respectively connected to the plurality of base bind pads; and

a plurality of solder balls respectively connecting the plurality of base TSVs to a substrate mounting the device.

6. The device of claim 5, wherein the buffer chip further comprises:

a serializer/deserializer (SERDES) receiving serial write data and providing serial read data via the plurality of base TSVs, and receiving parallel read data and providing parallel write data via the plurality of base bond pads.

7. The device of claim 6, wherein the buffer chip further comprises:

circuitry buffering a clock signal, a command signal, and an address signal received from the substrate and communicating buffered versions of the clock signal, the command signal, and the address signal to the first and second memory chips.

8. The device of claim 5, wherein the first and second memory chips are memory core chips and the buffer chip is an interface chip,

wherein the interface chip comprises

a serializer/deserializer (SERDES) receiving serial write data and providing serial read data via the plurality of base TSVs, and receiving parallel read data and providing parallel write data via the plurality of base bond pads;

and

a logic control circuit receiving an external clock signal, an external command signal, and an external address signal, generating an internal clock signal, an internal command signal, and an internal address signal, and communicating the internal clock signal, internal command signal, and internal address signal to the first and second memory chips.

9. The device of claim 1, wherein the first memory chip is seated face down on the first interposer chip.

10. The device of claim 1, wherein the first memory chip comprises a plurality of internal TSVs respectively connected to the second bond pads and the first memory chip is seated face up on the first interposer chip.

11. The device of claim 1, wherein the vertical connection elements are solder balls.

12. A semiconductor memory device comprising:

a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip;

each one of the stacked plurality of interposer chips comprising a central portion comprising bond pads seating the corresponding memory device and a peripheral portion comprising a plurality of through silicon vias (TSVs),

wherein the respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

13. The device of claim 12, wherein each interposer chip further comprises a plurality of distribution lines respectively connecting the bond pads to the plurality of TSVs.

14. The device of claim 12, wherein each memory chip is a bare semiconductor die or packaged semiconductor die.

15. The device of claim 12, wherein each memory chip is a memory core chip.

16. The device of claim 12, wherein the buffer chip further comprises:

a plurality of base TSVs respectively connected to the plurality of base bind pads; and

a plurality of solder balls respectively connecting the plurality of base TSVs to a substrate mounting the device.

17. The device of claim 16, wherein the buffer chip further comprises:

a serializer/deserializer (SERDES) receiving serial write data and providing serial read data via the plurality of base TSVs, and receiving parallel read data and providing parallel write data via the plurality of base bond pads.

18. The device of claim 17, wherein the buffer chip further comprises:

circuitry buffering a clock signal, a command signal, and an address signal received from the substrate and communicating buffered versions of the clock signal, the command signal, and the address signal to the first and second memory chips.

19. The device of claim 16, wherein the memory chips are memory core chips and the buffer chip is an interface chip,

wherein the interface chip comprises

a serializer/deserializer (SERDES) receiving serial write data and providing serial read data via the plurality of base TSVs, and receiving parallel read data and providing parallel write data via the plurality of base bond pads;

and

a logic control circuit receiving an external clock signal, an external command signal, and an external address signal, generating an internal clock signal, an internal command signal, and an internal address signal, and communicating the internal clock signal, internal command signal, and internal address signal to the memory chips.

20. The device of claim 12, wherein each memory chip is seated face down on the corresponding interposer chip.

21. The device of claim 12, wherein each memory chip comprises a plurality of internal TSVs respectively connected to the bond pads and wherein each memory chip is seated face up on the corresponding interposer chip.

22. The device of claim 12, wherein the vertical connection elements are solder balls.