Wafer level stacked packages with individual chip selection

• US 20090039528A1
• Filed: 08/07/2008
• Published: 02/12/2009
• Est. Priority Date: 08/09/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Mohammed, Ilyas, Haba, Belgacem
• Granted Patent: US 8,043,895 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads.

Claims

1. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:

a) providing first and second microelectronic substrates each including a plurality of microelectronic elements attached together at dicing lanes, each of said plurality of microelectronic elements including a first edge and a second edge remote from said first edge, each of said plurality of microelectronic elements further including contacts and traces extending from said contacts to identical locations proximate said first and second edges;

b) stacking and joining said first and second microelectronic substrates in first and second different orientations to form a stacked assembly such that said first edges of said microelectronic elements of said first microelectronic substrate are aligned with said second edges of said microelectronic elements of said second microelectronic substrate;

c) exposing said traces at said first and second edges of said microelectronic elements of said first and second microelectronic substrates, respectively; and

d) forming first and second leads, said first leads connected to said exposed traces of said microelectronic elements of said first microelectronic substrate, said second leads connected to said exposed traces of said microelectronic elements of said second microelectronic substrate, said second leads being electrically isolated from said first leads.

2. A method of fabricating a stacked assembly as claimed in claim 1, wherein said first and second edges of each said microelectronic element are remote from each other.

3. A method of fabricating a stacked assembly as claimed in claim 2, wherein said first and second leads extend in parallel paths along said first edges of said first microelectronic elements.

4. A method as claimed in claim 3, further comprising severing said stacked assembly along said first and second edges into a plurality of unit assemblies each including at least one of said first microelectronic elements and at least one of said second microelectronic elements.

5. A method of fabricating a stacked assembly as claimed in claim 1, wherein each of said microelectronic elements has north-south edges and east-west edges, wherein said traces extend from contacts adjacent to said north-south edges towards said east-west edges.

6. A method of fabricating a stacked assembly as claimed in claim 2, wherein each of said microelectronic elements has north-south edges and east-west edges, said east-west edges including said first and second edges, wherein said traces extend from contacts adjacent to said north-south edges towards said east-west edges.

7. A method of fabricating a stacked assembly as claimed in claim 2, wherein said first and second leads extend in parallel paths along at least said first and second edges of said plurality of edges.

8. A method of fabricating a stacked assembly as claimed in claim 2, wherein first faces of said microelectronic elements of said first and second microelectronic substrates confront each other.

9. A method of fabricating a stacked assembly as claimed in claim 2, further comprising aligning and joining a third microelectronic substrate with said first and second microelectronic substrates, said third microelectronic substrate having a third orientation different from said first and second orientations, wherein third traces extending along first faces of third microelectronic elements of said third microelectronic substrate extend in interleaved paths with said first and second traces of said microelectronic elements of said first and second microelectronic substrates, and said stacked assembly further includes third leads connected to said third traces, respectively, said third leads extending along said first and second edges and being interleaved with and electrically isolated from said first and second leads.

10. A method of fabricating a stacked assembly as claimed in claim 9, further comprising aligning and joining a fourth microelectronic substrate with said first, second and third microelectronic substrates, said fourth microelectronic substrate having a fourth orientation different from said first, second and third orientations, wherein fourth traces extending along first faces of said microelectronic elements of said fourth microelectronic substrate extend in interleaved paths with said first, second and third traces, and said stacked assembly further includes fourth leads connected to said fourth traces, said fourth leads extending along said first and second edges and being interleaved with and electrically isolated from said first, second and third leads.

11. A method of fabricating a stacked assembly as claimed in claim 10, wherein said first faces of said microelectronic elements of first, second, third and fourth microelectronic substrates each have the same width and each have the same length.

12. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:

a) providing a plurality of microelectronic substrates, each said microelectronic substrate including a plurality of like microelectronic elements each having a face and first and second edges extending away from said face, each of said microelectronic elements having contacts at said face and traces extending along said face from said contacts to locations proximate said first and second edges, said traces of each said microelectronic element extending in a lengthwise direction and being spaced apart in a lateral direction, transverse to said lengthwise direction;

b) stacking and joining said plurality of microelectronic substrates in different orientations such that said first edges of said microelectronic elements of a first one of said microelectronic substrates are aligned with corresponding second edges of said microelectronic elements of each other of said plurality of stacked and joined microelectronic substrates and each of said traces of said microelectronic elements of said first microelectronic substrate at said first edges is spaced laterally from each of said traces of said microelectronic elements of any other of said stacked and joined microelectronic substrates.

13. A method of fabricating a stacked assembly as claimed in claim 12, further comprising:

c) exposing said traces at said first and second edges of said microelectronic elements of said plurality of stacked, joined microelectronic substrates; and

d) forming leads, said leads connected to said exposed traces of said microelectronic elements of said stacked, joined microelectronic substrates.

14. A method of fabricating a stacked assembly as claimed in claim 13, wherein said leads extend in parallel paths along said first edges of said microelectronic elements.

15. A method of fabricating a stacked assembly as claimed in claim 13, wherein step (b) includes stacking and joining first, second and third substrates having first, second and third different orientations and step (d) includes forming first leads connected to first traces of said microelectronic elements of said first microelectronic substrate, second leads connected to second traces of said microelectronic elements of said second microelectronic substrate, and third leads connected to third traces of said microelectronic elements of said third microelectronic substrate, respectively, wherein at least some of said leads of each of said first, second and third microelectronic substrates are electrically isolated from said leads of any other of said first, second and third microelectronic substrates.

16. A method of fabricating a stacked assembly as claimed in claim 13, wherein step (b) includes stacking and joining first, second, third and fourth substrates having first, second, third and fourth different orientations and step (d) includes forming first leads connected to first traces of said microelectronic elements of said first microelectronic substrate, second leads connected to second traces of said microelectronic elements of said second microelectronic substrate, third leads connected to third traces of said microelectronic elements of said third microelectronic substrate, and fourth leads connected to fourth traces of said microelectronic elements of said fourth microelectronic substrate, wherein at least some of said leads of each of said first, second, third and fourth microelectronic substrates are electrically isolated from said leads of any other of said first, second, third and fourth microelectronic substrates.

17. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:

a) providing a plurality of microelectronic substrates, each of said microelectronic substrates including a plurality of microelectronic elements attached together at edges defined by dicing lanes, said edges including first and second edges, each of said microelectronic elements having a face extending between said first and second edges, each said microelectronic substrate having bond pads at said face and redistribution traces extending along said face from said bond pads towards said first and second edges, said redistribution traces of each said microelectronic substrate having a pitch, said pitch being greater than a number N multiplied by a width of said redistribution traces at said first edge, N being greater than two, said redistribution traces at said first edge being offset from said redistribution traces at said second edge in a direction of said pitch of said redistribution traces;

b) stacking a second one of said microelectronic substrates in a first orientation onto a first one of said microelectronic substrates in a second orientation such that said redistribution traces at said first edge of each microelectronic element of said first microelectronic substrate are offset from said redistribution traces of each corresponding microelectronic element of said second microelectronic substrate directly overlying said microelectronic element of said first microelectronic substrate;

c) forming leads connected to said redistribution traces, said leads extending about said first and second edges of said microelectronic elements of said first and second microelectronic substrates; and

d) dicing said stacked first and second microelectronic substrates along said dicing lanes into individual stacked assemblies having first and second edges, wherein closest adjacent leads at said first edges are laterally spaced from each other.

18. A stacked assembly including first and second stacked microelectronic elements, each of said first and second microelectronic elements having a first face, edges extending away from said first face and a plurality of traces extending along said first face towards said edges, wherein said first and second microelectronic elements have first and second different orientations, wherein at least some first traces of said first microelectronic element are electrically isolated from at least some second traces of said second microelectronic element, and

said stacked assembly further includes first and second leads connected to said first and second traces, respectively, said first and second leads extending along said edges.

19. A stacked assembly as claimed in claim 18, wherein said first and second leads extend in parallel paths along at least some aligned edges of said plurality of edges.

20. A stacked assembly as claimed in claim 18, wherein said first faces of said microelectronic elements confront each other.

21. A stacked assembly as claimed in claim 18, further comprising a third microelectronic element stacked in alignment with said first and second microelectronic elements, said third microelectronic element having a third orientation different from said first and second orientations, wherein at least some third traces extend along a first face of said third microelectronic element and are electrically isolated from at least some of said first and said second traces of said first and second microelectronic elements, and said stacked assembly further includes third leads connected to said third traces, said third leads extending along said edges and being electrically isolated from said first and second leads.

22. A stacked assembly as claimed in claim 21, further comprising a fourth microelectronic element stacked in alignment with said first, second and third microelectronic elements, said fourth microelectronic element having a fourth orientation different from said first, second and third orientations, wherein at least some fourth traces extend along a first face of said fourth microelectronic element and are electrically isolated from at least some of said first, second and third traces, and

said stacked assembly further includes fourth leads connected to said fourth traces, said fourth leads extending along said edges and being electrically isolated from said first, second and third leads.

23. A stacked assembly as claimed in claim 22, wherein said first faces of each of said first, second, third and fourth microelectronic elements has the same width and each said face has the same length.

24. A stacked assembly as claimed in claim 18, wherein each of said first and second microelectronic elements has north-south edges and east-west edges, wherein said traces extend from contacts adjacent to said north-south edges towards said east-west edges.