Method of Acceptance for Semiconductor Devices

• US 20090039912A1
• Filed: 08/10/2007
• Published: 02/12/2009
• Est. Priority Date: 08/10/2007
• Status: Active Grant

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: McMahon, Robert, Goss, John R., Habib, Nazmul, Bickford, Jeanne Paulette Spence
• Granted Patent: US 7,560,946 B2
• Time in Patent Office: Days
• US Class Current: 324/750.300
• CPC Class Codes: G01R 31/2648 Characterising semiconductor materials testing of materials or semi-finished products G01R31/2831; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric acceptance criteria. An on-chip parametric measurement macro is included in a design of each semiconductor chip for each identified on-chip parametric measurement structure. Each on-chip parametric measurement macro is tested to determine compliance of the semiconductor chip to the set of parametric acceptance criteria. Compliance to the set of parametric acceptance criteria is validated.

Claims

1. A method of accepting semiconductor chips using on-chip parametric measurements, the method comprising:

determining an on-chip parametric measurement structure for each parameter in a set of parametric acceptance criteria;

including an on-chip parametric measurement macro in a design of each semiconductor chip for each identified on-chip parametric measurement structure;

testing each on-chip parametric measurement macro to determine compliance of the semiconductor chip to the set of parametric acceptance criteria; and

validating the compliance to the set of parametric acceptance criteria.

2. The method of claim 1 wherein the set of parametric acceptance criteria is established by

identifying parametric acceptance criteria for each semiconductor chip;

and

documenting the identified parametric acceptance criteria.

3. The method of claim 1 wherein including the on-chip parametric measurement macro comprises:

including a scaling parametric measurement (SPM) macro in the design of the semiconductor chip for each identified on-chip parametric measurement structure.

4. The method of claim 1 wherein testing each on-chip parameter measurement macro comprises:

testing each on-chip parametric measurement macro to determine compliance of the semiconductor chip to the set of parametric acceptance criteria in a wafer-level test.

5. The method of claim 1 wherein testing each on-chip parameter measurement macro comprises:

testing each on-chip parametric measurement macro to determine compliance of the semiconductor chip to the set of parametric acceptance criteria in a module-level test.

6. The method of claim 1 wherein validating the compliance is performed by a designer of the semiconductor chip.

7. The method of claim 1 further comprising:

using the on-chip parametric measurement macros to debug a design issue.