Systems and Apparatus for Providing a Multi-Mode Memory Interface

• US 20090039916A1
• Filed: 08/07/2007
• Published: 02/12/2009
• Est. Priority Date: 08/07/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Weiss, Jonas R., Toifl, Thomas H., Menolfi, Christian I., Schmatz, Martin L., Buchmann, Peter
• Application Number:
  US11/834,926
• Publication Number:
  US 20090039916A1
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary embodiment provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter.

Claims

1. An integrated circuit having one or multiple modes of operation, the integrated circuit comprising:

a pair of terminal input/output pins;

a pair of T-coil circuits, wherein each pin is connected to a node of an individual T-coil circuit, wherein the individual T-coil circuit comprises a pair of serially connected inductors and a bridging capacitor forming three nodes, wherein at least one node is connected to the terminal input/output pin, a middle tap connected to a capacitive load, and a third node connected to a resistive load;

said capacitive load comprising an electrostatic discharge diode and a plurality of thick-oxide switches connecting at least one of a power or ground;

a DDR2/DDR3 (double data rate two or three) interface; and

a high-speed differential receiver circuit; and

said resistive load comprising a plurality of thick-oxide switches connecting a high-speed differential driver, wherein the plurality of thick-oxide switches are used to select the mode of operation of the integrated circuit, and wherein the T-coil circuit is used to compensate for parasitic capacitances.

2. An integrated circuit according to claim 1, wherein the integrated circuit functions in a power or ground mode when the thick-oxide switches connected to the power or ground are closed, and

wherein the integrated circuit functions in a non-connected or high-impedance mode when all of the thick-oxide switches are open and the DDR2/DDR3 interface is in a high-impedance state.

3. An integrated circuit according to claim 2, wherein the integrated circuit functions in a DDR2/DDR3 interface mode when all of the thick-oxide switches are open.

4. An integrated circuit according to claim 1, wherein the integrated circuit functions as a high-speed differential driver when all thick oxide switches above and below the high-speed differential driver section are closed and all other thick oxide switches are open.

5. An integrated circuit according to claim 1, wherein the integrated circuit functions as a high-speed differential receiver when all thick oxide switches above and below the high-speed differential driver section are closed, all thick oxide switches above and in front of the high-speed differential receiver are closed, and all other thick oxide switches are open.

6. A system for an integrated circuit having one or multiple modes of operation, the integrated circuit comprising:

a pair of terminal input/output pins;

a pair of T-coil circuits, wherein each pin connects to a node of an individual T-coil circuit, wherein the individual T-coil circuits comprise a pair of serially connected coupled inductors and a bridging capacitor forming three nodes, wherein at least one node is connected to the terminal input/output pin, a middle tap connected to a capacitive load, and a third node connected to a resistive load;

the capacitive load comprising an electrostatic discharge diode and a plurality of thick-oxide switches connecting at least one of a power or ground;

a DDR2/DDR3 interface; and

a high-speed differential receiver circuit;

the resistive load comprising a plurality of thick-oxide switches connecting a high-speed differential driver, wherein the plurality of thick-oxide switches are used to select the mode of operation of the integrated circuit, and wherein the T-coil circuit is used to compensate parasitic capacitances.