Programmable Interconnect Structures
First Claim
1. A programmable interconnect structure to couple a first node to a second node of an integrated circuit comprising:
- a pass-gate to electrically couple the first node to the second node fabricated on a substrate layer; and
a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer, wherein changing data stored in the memory element provides a programmable method to achieve one of;
isolate said first node from said second node; and
couple said first node to said second node.
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Accused Products
Abstract
A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes.
A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.
A method of forming a programmable interconnect structure for an integrated circuit comprises: fabricating one or more pass-gates on a substrate layer to electrically connect two points; and selectively fabricating either a memory circuit or a conductive pattern substantially above said pass-gates to control a portion of said pass-gates; and fabricating an interconnect and routing layer substantially above said memory circuits to connect said pass-gates and one of said memory circuits and conductive pattern.
90 Citations
20 Claims
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1. A programmable interconnect structure to couple a first node to a second node of an integrated circuit comprising:
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a pass-gate to electrically couple the first node to the second node fabricated on a substrate layer; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer, wherein changing data stored in the memory element provides a programmable method to achieve one of; isolate said first node from said second node; and couple said first node to said second node. - View Dependent Claims (2, 3, 4, 5)
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6. A programmable interconnect structure for an integrated circuit comprising:
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a pass-gate to electrically connect two nodes; and a configurable memory circuit comprising one of; a user configurable memory element for a user to program a desired state; and a mask configurable memory element to permanently fix a desired state; and an interconnect and routing layer substantially above said pass-gates to connect said pass-gate and said configurable memory circuit; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes by changing data in the configurable memory circuit. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A programmable interconnect structure for an integrated circuit comprising:
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a plurality of pass-gates to electrically couple a plurality of nodes; and a configurable memory circuit comprising either user configurable memory elements or mask configurable memory elements to identify desired memory states; and one or more interconnect and routing layers to couple; said plurality of pass-gate to said plurality of nodes; and said plurality of pass-gates to said configurable memory circuit; wherein, identifying the desired memory states select the interconnect pattern between the plurality of nodes without altering the layout of said plurality of pass-gates and the locations of the plurality of nodes. - View Dependent Claims (17, 18, 19, 20)
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Specification