VARIABLE DELAY CIRCUIT, TESTING APPARATUS, AND ELECTRONIC DEVICE

• US 20090039939A1
• Filed: 09/19/2008
• Published: 02/12/2009
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: SATOSHI, SUDOU, HASUMI, TAKUYA, SUDA, MASAKATSU
• Granted Patent: US 7,755,407 B2
• Time in Patent Office: Days
• US Class Current: 327/281
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00078 Fixed delay
• CPC Class Codes: H03K 2005/00215 where the conduction path of multiple FET's is in parallel or in series, all having the same gate control
• CPC Class Codes: H03K 2005/00221 where the conduction path of the different output FET's is connected in parallel with different gate control, e.g. having different sizes or thresholds, or coupled through different resistors
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal.

Claims

1. A variable delay circuit that outputs an output signal delayed with respect to an input signal by a designated delay time, comprising:

a delay controller that outputs a control voltage according to a set value of the delay time;

a power current controlling MOS transistor that receives the control voltage at a gate thereof, and outputs a drain power current according to the control voltage;

a correction section that is connected in parallel to a source and a drain of the power current controlling MOS transistor, and outputs a correction power current on a monotonic decrease as the drain power current increases in a range larger than a predetermined boundary power current within a normal usage range of the drain power current; and

a delay element that runs an output power current resulting from adding the correction power current to the drain power current, between the delay element and an output terminal of the variable delay circuit, and outputs the output signal delayed by a time according to the output power current, when changing a signal value of the output signal according to the input signal.

2. The variable delay circuit according to claim 1, wherein

the delay controller outputs a positive control voltage that is higher when a set value of the delay time is larger, and a negative control voltage that is lower when the set value of the delay time is larger,

wherein the variable delay circuit comprises:

a power current controlling pMOS transistor being the power current controlling MOS transistor that receives the positive control voltage at a gate thereof and outputs a positive drain power current according to the positive control voltage;

a power current controlling nMOS transistor being the power current controlling MOS transistor that receives the negative control voltage at a gate thereof, and outputs a negative drain power current according to the negative control voltage;

a positive correction section being the correction section that is connected in parallel to a source and a drain of the power current controlling pMOS transistor and outputs a positive correction power current on a monotonic decrease as the drain power current increases in a range larger than the boundary power current within a normal usage range of the positive drain power current; and

a negative correction section being the correction section that is connected in parallel to a source and a drain of the power current controlling nMOS transistor and outputs a negative correction power current on a monotonic decrease as the drain power current increases in a range larger than the boundary power current within a normal usage range of the negative drain power current, and wherein

in causing a signal value of the output signal to rise according to the input signal, the delay element outputs, from the output terminal of the variable delay circuit, a positive output power current resulting from adding the correction power current to the positive drain power current, thereby outputting a rising edge of the output signal delayed by a time according to the positive output power current, and

in causing a signal value of the output signal to fall according to the input signal, the delay element runs, in the output terminal of the variable delay circuit, a negative output power current resulting from adding the correction power current to the negative drain power current, thereby outputting a falling edge of the output signal delayed by a time according to the negative output power current.

3. The variable delay circuit according to claim 2, wherein

the source of the power current controlling pMOS transistor connects to a positive power supply terminal,

the drain of the power current controlling pMOS transistor connects to a positive power supply input terminal of the delay element,

the source of the power current controlling nMOS transistor connects to a negative power supply terminal, and

the drain of the power current controlling nMOS transistor connects to a negative power supply input terminal of the delay element.

4. The variable delay circuit according to claim 2, wherein

each of the power current controlling pMOS transistor and the power current controlling nMOS transistor is such that the source and the drain thereof are connected between an output terminal of the delay element and an output terminal of the variable delay circuit.

5. The variable delay circuit according to claim 2, further comprising:

an additional pMOS transistor of a diode connection type that is connected in parallel to the source and the drain of the power current controlling pMOS transistor, and that has a gate connected to the drain of the power current controlling pMOS transistor; and

an additional nMOS transistor of a diode connection type that is connected in parallel to the source and the drain of the power current controlling nMOS transistor, and that has a gate connected to the drain of the power current controlling nMOS transistor.

6. The variable delay circuit according to claim 2, wherein

the positive correction section includes two pMOS transistors,

the two pMOS transistors are connected in series with each other in terms of source/drain, one gate receiving the positive control voltage, and the other gate receiving the negative control voltage, and

the two pMOS transistors connected in series with each other are connected in parallel to the power current controlling pMOS transistor.

7. The variable delay circuit according to claim 2, wherein

the negative correction section includes two nMOS transistors,

the two nMOS transistors are connected in series with each other in terms of source/drain, one gate receiving the negative control voltage, and the other gate receiving the positive control voltage, and

the two nMOS transistors connected in series with each other are connected in parallel to the power current controlling nMOS transistor.

8. A test apparatus for testing an electronic device, the test apparatus comprising:

a pattern generator that generates a test pattern for testing the electronic device;

a waveform shaper that shapes the test pattern and supplies the shaped test pattern to the electronic device; and

a timing generator that outputs a timing signal for controlling a timing at which the waveform shaper supplies the test pattern to the electronic device, wherein

the timing generator includes;

a delay controller that outputs a control voltage according to a designated value of a delay time designated by the test pattern to delay a reference clock;

a power current controlling MOS transistor that receives the control voltage at a gate thereof, and outputs a drain power current according to the control voltage;

a correction section that is connected in parallel to a source and a drain of the power current controlling MOS transistor and outputs a correction power current, the correction power current increasing monotonically as the drain power current increases in a range smaller than a predetermined boundary power current within a normal usage range of the drain power current, and decreasing monotonically as the drain power current increases in a range larger than the boundary power current; and

a delay element that runs, between the delay element and an output terminal of the timing generator, an output power current resulting from adding the correction power current to the drain power current, thereby outputting the timing signal delayed with respect to the reference clock by a time according to the output power current, in changing a signal value of an output signal according to an input signal.

9. An electronic device comprising:

a circuit under test; and

a test circuit for testing the circuit under test, wherein

the test circuit includes;

a pattern generator that generates a test pattern for testing the circuit under test;

a waveform shaper that shapes the test pattern and supplies the shaped test pattern to the circuit under test; and

a timing generator that outputs a timing signal for controlling a timing at which the waveform shaper supplies the test pattern to the circuit under test, and wherein

the timing generator includes;

a delay controller that outputs a control voltage according to a designated value of a delay time designated by the test pattern to delay a reference clock;

a power current controlling MOS transistor that receives the control voltage at a gate thereof, and outputs a drain power current according to the control voltage;

a correction section that is connected in parallel to a source and a drain of the power current controlling MOS transistor and outputs a correction power current, the correction power current increasing monotonically as the drain power current increases in a range smaller than a predetermined boundary power current within a normal usage range of the drain power current and decreasing monotonically as the drain power current increases in a range larger than the boundary power current; and

a delay element that runs, between the delay element and an output terminal of the timing generator, an output power current resulting from adding the correction power current to the drain power current, thereby outputting the timing signal delayed with respect to the reference clock by a time according to the output power current, in changing a signal value of an output signal according to an input signal.

10. A variable delay circuit for outputting an output signal delayed with respect to an input signal by a designated delay time, comprising:

a delay controller that outputs a control signal according to a set value of the delay time;

a power current controller that is coupled with an output terminal of the delay controller, receives a control signal outputted from the delay controller, and outputs a driving power current based on the control signal; and

a delay element that includes a signal input terminal for receiving the input signal, a power supply input terminal for receiving and outputting the power current, and a signal output terminal for outputting an output signal delayed by a time according to the driving power current.