SEMICONDUCTOR MEMORY DEVICE, MEMORY-MOUNTED LSI AND FABRICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE

• US 20090040802A1
• Filed: 07/21/2008
• Published: 02/12/2009
• Est. Priority Date: 08/07/2007
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Arakawa, Ken
• Application Number:
  US12/176,633
• Publication Number:
  US 20090040802A1
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

The semiconductor memory device includes a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines. A plurality of MOS transistor blocks are provided which are same in the configuration of circuit elements and include MOS transistors as one kind of the circuit elements. In part of the plurality MOS transistor blocks, the MOS transistors are used for drive of the word lines or the bit lines, while in at least part of the remaining MOS transistor blocks, the MOS transistors are used as MOS capacitors.

Claims

1. A semiconductor memory device comprising:

a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines; and

a plurality of MOS transistor blocks same in the configuration of circuit elements, MOS transistors being included as one kind of the circuit elements,

wherein in part of the plurality of MOS transistor blocks, the MOS transistors are used for drive of the plurality of word lines or the plurality of bit lines, and in at least part of the remaining MOS transistor blocks, the MOS transistors are used as MOS capacitors.

2. The device of claim 1, further comprising wiring capacitors of a number corresponding to the number of stages of the memory cell arrays.

3. The device of claim 1, wherein a guard band is placed between a well for MOS transistors used for drive of the plurality of word lines or the plurality of bit lines and a well for MOS transistors used as MOS capacitors.

4. The device of claim 1, further comprising an input/output circuit having MOS transistors and connected with external terminals,

wherein the MOS transistors of the input/output circuit are the same in gate oxide film thickness as the MOS transistors in the MOS transistor blocks, and

the MOS capacitors are connected with power supply for the input/output circuit

5. The device of claim 1, wherein the memory cells are memory cells using ferromagnetic tunneling magneto-resistance.

6. The device of claim 1, wherein the memory cells are resistive memory cells that store data with resistance change.

7. The device of claim 1, wherein the memory cells are memory cells using an antifuse.

8. The device of claim 1, wherein predetermined voltages are supplied to the terminals of each of the MOS transistors used as MOS capacitors via a wiring layer.

11. A memory-mounted LSI comprising:

the semiconductor memory device of claim 1; and

a circuit operating in response to data stored in the semiconductor memory device.

12. An audio apparatus incorporating the semiconductor memory device of claim 1.

13. An automobile incorporating the audio apparatus of claim 12.

9. A fabrication method for a semiconductor memory device including a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines, the semiconductor memory device being expanded to product types different in capacity depending on the number of stages of memory cell arrays, the method comprising:

a lower layer formation step of forming a plurality of MOS transistor blocks same in the configuration of circuit elements and including MOS transistors as one kind of the circuit elements in a lower layer;

a wiring layer formation step of executing a first sub-step of wiring the terminals of each of the MOS transistors in a wiring layer so that all of the plurality of MOS transistor blocks drive the plurality of word lines or the plurality of bit lines in fabrication of a product type maximum in capacity among the product types, and executing a second sub-step of wiring the terminals of each of the MOS transistors in the wiring layer so that the MOS transistors drive the plurality of word lines or the plurality of bit lines in part of the plurality of MOS transistor blocks and wiring the terminals of each of the MOS transistors in the wiring layer so that the MOS transistors function as MOS capacitors in at least part of the remaining MOS transistor blocks in fabrication of a product type other than the product type maximum in capacity among the product types; and

a memory cell array addition step of, in the case of requiring an additional memory cell array, stacking a desired number of additional wiring layers including the memory cell array on the wiring layer.

10. The method of claim 9, wherein the wiring layer formation step further includes forming wiring capacitors of a number based on the number of stages of memory cell arrays.

14. A semiconductor memory device comprising a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines, the semiconductor memory device being expanded to product types different in capacity depending on the number of stages of memory cell arrays,

wherein the semiconductor memory device further comprises a plurality of MOS transistor blocks same in the configuration of circuit elements and including MOS transistors as one kind of the circuit elements,

for a product type maximum in capacity among the product types, all of the plurality of MOS transistor blocks are used for drive of the plurality of word lines or the plurality of bit lines, and

for a product type other than the product type maximum in capacity among the product types, the MOS transistors are used for drive of the plurality of word lines or the plurality of bit lines in part of the plurality of MOS transistor blocks while the MOS transistors are used as MOS capacitors in at least part of the remaining MOS transistor blocks.