SEMICONDUCTOR MEMORY DEVICE, MEMORY-MOUNTED LSI AND FABRICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A semiconductor memory device comprising:
- a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines; and
a plurality of MOS transistor blocks same in the configuration of circuit elements, MOS transistors being included as one kind of the circuit elements,wherein in part of the plurality of MOS transistor blocks, the MOS transistors are used for drive of the plurality of word lines or the plurality of bit lines, and in at least part of the remaining MOS transistor blocks, the MOS transistors are used as MOS capacitors.
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Accused Products
Abstract
The semiconductor memory device includes a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines. A plurality of MOS transistor blocks are provided which are same in the configuration of circuit elements and include MOS transistors as one kind of the circuit elements. In part of the plurality MOS transistor blocks, the MOS transistors are used for drive of the word lines or the bit lines, while in at least part of the remaining MOS transistor blocks, the MOS transistors are used as MOS capacitors.
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Citations
14 Claims
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1. A semiconductor memory device comprising:
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a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines; and a plurality of MOS transistor blocks same in the configuration of circuit elements, MOS transistors being included as one kind of the circuit elements, wherein in part of the plurality of MOS transistor blocks, the MOS transistors are used for drive of the plurality of word lines or the plurality of bit lines, and in at least part of the remaining MOS transistor blocks, the MOS transistors are used as MOS capacitors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 11, 12, 13)
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9. A fabrication method for a semiconductor memory device including a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines, the semiconductor memory device being expanded to product types different in capacity depending on the number of stages of memory cell arrays, the method comprising:
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a lower layer formation step of forming a plurality of MOS transistor blocks same in the configuration of circuit elements and including MOS transistors as one kind of the circuit elements in a lower layer; a wiring layer formation step of executing a first sub-step of wiring the terminals of each of the MOS transistors in a wiring layer so that all of the plurality of MOS transistor blocks drive the plurality of word lines or the plurality of bit lines in fabrication of a product type maximum in capacity among the product types, and executing a second sub-step of wiring the terminals of each of the MOS transistors in the wiring layer so that the MOS transistors drive the plurality of word lines or the plurality of bit lines in part of the plurality of MOS transistor blocks and wiring the terminals of each of the MOS transistors in the wiring layer so that the MOS transistors function as MOS capacitors in at least part of the remaining MOS transistor blocks in fabrication of a product type other than the product type maximum in capacity among the product types; and a memory cell array addition step of, in the case of requiring an additional memory cell array, stacking a desired number of additional wiring layers including the memory cell array on the wiring layer. - View Dependent Claims (10)
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14. A semiconductor memory device comprising a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines, the semiconductor memory device being expanded to product types different in capacity depending on the number of stages of memory cell arrays,
wherein the semiconductor memory device further comprises a plurality of MOS transistor blocks same in the configuration of circuit elements and including MOS transistors as one kind of the circuit elements, for a product type maximum in capacity among the product types, all of the plurality of MOS transistor blocks are used for drive of the plurality of word lines or the plurality of bit lines, and for a product type other than the product type maximum in capacity among the product types, the MOS transistors are used for drive of the plurality of word lines or the plurality of bit lines in part of the plurality of MOS transistor blocks while the MOS transistors are used as MOS capacitors in at least part of the remaining MOS transistor blocks.
Specification