SEMICONDUCTOR MEMORY DEVICE

• US 20090040807A1
• Filed: 08/05/2008
• Published: 02/12/2009
• Est. Priority Date: 08/06/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takashima, Daisaburo, DOUMAE, Sumiko
• Granted Patent: US 7,791,922 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A semiconductor memory device comprises a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit. The control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading.

Claims

1. A semiconductor memory device, comprising:

a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor;

a sense amp circuit operative to sense/amplify a signal read out of said ferroelectric capacitor through a pair of bit lines;

a pair of decoupling transistors provided on said pair of bit lines to decouple said bit lines;

a control circuit operative to provide a control signal to the gates of said decoupling transistors to control conduction of said decoupling transistors; and

a dummy capacitor provided in connection with at least either one of said pair of bit lines between said decoupling transistors and said sense amp circuit,

wherein said control circuit is configured to be capable of turning said decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading.

2. The semiconductor memory device according to claim 1, further comprising a potential control circuit operative to control the potentials on said pair of bit lines between said decoupling transistors and said sense amp circuit via said dummy capacitor,

wherein said potential control circuit is configured to charge one of said pair of bit lines after said decoupling transistors are turned from on to off.

3. The semiconductor memory device according to claim 1, wherein said control circuit is configured to be capable of keeping said decoupling transistors turned on during reading in a first mode while turning said decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading in a second mode.

4. The semiconductor memory device according to claim 3, further comprising a potential control circuit operative to control the potentials on said pair of bit lines via said dummy capacitor between said decoupling transistors and said sense amp circuit,

wherein said potential control circuit is configured to charge one of said pair of bit lines after said decoupling transistors are turned from on to off in said second mode.

5. The semiconductor memory device according to claim 1, wherein said dummy capacitor is one of a pair of dummy capacitors provided in connection with said pair of bit lines.

6. The semiconductor memory device according to claim 1, wherein said dummy capacitor has one end connected to both of said pair of bit lines.

7. The semiconductor memory device according to claim 1, further comprising connection transistors provided between said dummy capacitor and said pair of bit lines and operative to switch between connection and disconnection between said pair of bit lines and said dummy capacitor.

8. The semiconductor memory device according to claim 7, further comprising a drive circuit operative to on/off-control said connection transistors,

wherein said drive circuit turns said connection transistors from off to on before said decoupling transistors are turned from on to off.

9. The semiconductor memory device according to claim 1, further comprising an inverter provided in connection with one end of said dummy capacitor on the side not connected to said pair of bit lines.

10. The semiconductor memory device according to claim 1, wherein said memory cell array comprises a plurality of memory cells each including said cell transistor and said ferroelectric connected in parallel,

wherein said plurality of memory cells are connected in series.

11. The semiconductor memory device according to claim 1, further comprising block selection transistors operative to control conduction between said memory cell array and said pair of bit lines.