METHOD AND SYSTEM FOR PROVIDING A SENSE AMPLIFIER AND DRIVE CIRCUIT FOR SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY

• US 20090040855A1
• Filed: 08/07/2007
• Published: 02/12/2009
• Est. Priority Date: 08/07/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation, Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation), Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Yu, David Chang-Cheng, Luo, Xiao
• Granted Patent: US 7,764,536 B2
• Time in Patent Office: Days
• US Class Current: 365/205
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods

Abstract

A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disablies at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.

Claims

1. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic element and at least one selection device, the at least one magnetic element being programmable using at least one write current driven through the magnetic element;

a plurality of bit lines corresponding to the plurality of magnetic storage cells;

at least one reference line for providing at least one reference signal;

at least one sense amplifier coupled with the plurality of bit lines and the at least one reference line, the at least one sense amplifier having logic and a plurality of stages, the plurality of stages including a first stage and a second stage, the first stage for converting at least one current signal to at least one differential voltage signal and the second stage for amplifying the at least one differential voltage signal, the logic for selectively disabling at least one of the first stage and the second stage in the absence of a read operation and enabling the first stage and the second stage during the read operation.

2. The magnetic memory of claim 1 wherein the logic further includes:

a plurality of transistors coupled between the first stage and the second stage; and

a plurality of transmission gates coupled between the first and second stages.

3. The magnetic memory of claim 2 wherein the first stage further includes:

a plurality of non-inverting gates; and

a plurality of inverting gates interleaved with the plurality of non-inverting gates.

4. The magnetic memory of claim 1 wherein the first stage further includes:

a first pair of current mirrored transistors;

a second pair of current mirrored transistors corresponding to the first pair of current mirrored transistors, the first pair of current mirrored transistors and the second pair of current mirrored transistors providing the at least one differential voltage signal.

5. The magnetic memory of claim 4 wherein the first stage further includes:

a first resistor coupled to the first pair of current mirrored transistors;

a second resistor coupled to the second pair of current mirrored transistors; and

an enabling transistor coupled to the first resistor and the second resistor, the enabling transistor for selectively enabling the first pair of current mirrored transistors and the second pair of current mirrored transistors.

6. The magnetic memory of claim 4 wherein the first stage further includes:

a first transistor coupled with the first pair of current mirrored transistors and a pre-charge voltage;

a second transistor coupled with the second pair of current mirrored transistors and the pre-charge voltage; and

a pre-charge circuit coupled between the inputs of first pair of current mirrored transistors and the second pair of current mirrored transistors.

7. The magnetic memory of claim 6 wherein the first stage further includes an additional transistor between inputs of the first pair of current mirrored transistors and the second pair of current mirrored transistors.

8. The magnetic memory of claim 4 wherein the first stage further includes:

a first transistor coupled to the first pair of current mirrored transistors;

a second transistor coupled to the second pair of transistors; and

an enabling transistor coupled to the first transistor and the second transistor, the enabling transistor for selectively enabling the first pair of current mirrored transistors and the second pair of current mirrored transistors.

9. The magnetic memory of claim 8 wherein the first stage further includes:

a first transistor coupled with the first pair of current mirrored transistors and a pre-charge voltage;

a second transistor coupled with the second pair of current mirrored transistors and the pre-charge voltage; and

a pre-charge circuit coupled between the inputs of the first pair and the second pair.

10. The magnetic memory of claim 9 wherein the first stage further includes an additional transistor between inputs of the first pair of current mirrored transistors and the second pair of current mirrored transistors.

11. The magnetic memory of claim 1 wherein the second stage further includes a plurality of transistors configured as a differential voltage sense amplifier.

12. The magnetic memory of claim 1 further comprising:

a plurality of source lines corresponding to the plurality of magnetic storage cells

at least one write driver coupled to the plurality of bit lines and the plurality of source lines, the write driver including a plurality of logic gates configured to selectively couple at least one of the plurality of bit lines to a first high voltage and at least one of the plurality of source lines to a first low voltage and to selectively the at least one of the plurality of bit lines to a second low voltage and the at least one of the plurality of source lines to a second high voltage.

13. The magnetic memory of claim 1 wherein the plurality of bit lines and the at least one reference line are configured to be selectively pre-charged to a pre-charge state before the sense amplifier is enabled.

14. The magnetic memory of claim 13 wherein the pre-charge state is ground.

15. The magnetic memory of claim 1 wherein the first stage includes a plurality of outputs, the magnetic memory further comprising:

a transistor coupled between the plurality of outputs, the transistor for equalizing the plurality of outputs prior to a read operation.

16. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic element and at least one selection device, the at least one magnetic element being programmable using at least one write current driven through the magnetic element;

a plurality of bit lines corresponding to the plurality of magnetic storage cells;

a plurality of source lines corresponding to the plurality of magnetic storage cells;

at least one reference line for providing at least one reference signal;

a sense amplifier coupled with the plurality of bit lines and at least one reference line, the at least one sense amplifier having logic and a plurality of stages, the plurality of stages including a first stage and a second stage, the first stage for converting at least one current signal to at least one differential voltage signal and the second stage for amplifying the at least one differential voltage signal, the logic for selectively disabling at least one of the first stage and the second stage in the absence of a read operation and enabling the first stage and the second stage during the read operation, the logic including a plurality of transistor coupled between the first stage and the second stage and a plurality of transmission gates coupled between the first and second stages, the first stage including a first pair of current mirrored transistors and a second pair of current mirrored transistors coupled with the first pair of current mirrored transistors, the first pair of current mirrored transistors and the second pair of current mirrored transistors providing the differential voltage signal, the first stage also including at least one of a resistor pair and a transistor pair, the resistor pair including a first resistor coupled to the first pair of current mirrored transistors and a second resistor, substantially identical to the first resistor, coupled to the second pair of current mirrored transistors, the first stage also including an enabling transistor coupled to the first resistor and the second resistor, the enabling transistor for selectively enabling the first stage and the second stage, the transistor pair including a first transistor coupled to the first pair of current mirrored transistors and a second transistor, substantially identical to the first transistor, coupled to the second pair of current mirrored transistors, the first stage also including an enabling transistor coupled to the first transistor and the second transistor, the enabling transistor for selectively enabling the first stage and the second stage.

17. A method for providing magnetic memory comprising:

providing a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic element and at least one selection device, the at least one magnetic element being programmable using at least one write current driven through the magnetic element;

providing a plurality of bit lines corresponding to the plurality of magnetic storage cells;

providing at least one reference line for providing at least one reference signal

providing at least one sense amplifier coupled with the plurality of bit lines and the at least one reference line, the at least one sense amplifier providing including providing logic and providing a plurality of stages, the plurality of stages providing including providing a first stage and providing a second stage, the first stage for converting at least one current signal to at least one differential voltage signal and the second stage for amplifying the at least one differential voltage signal, the logic for selectively disabling at least one of the first stage and the second stage in the absence of a read operation and enabling the first stage and the second stage during the read operation.

18. The method of claim 17 wherein the logic providing further includes:

providing a plurality of transistor coupled between the first stage and the second stage; and

providing a plurality of transmission gates coupled between the first and second stages.

19. The method of claim 18 wherein the first stage providing further includes:

providing a plurality of non-inverting gates; and

providing a plurality of inverting gates interleaved with the plurality of non-inverting gates.

20. The method of claim 17 wherein the first stage providing further includes:

providing a first pair of current mirrored transistors;

providing a second pair of current mirrored transistors coupled with the first pair of current mirrored transistors, the first pair of current mirrored transistors and the second pair of current mirrored transistors providing the at least one differential voltage signal.

21. The method of claim 20 wherein the first stage providing further includes:

providing a first resistor coupled to the first pair of current mirrored transistors;

providing a second resistor coupled to the second pair of current mirrored transistors; and

providing an enabling transistor coupled to the first resistor and the second resistor, the enabling transistor for selectively enabling the first stage and the second stage.

22. The method of claim 17 wherein the first stage providing further includes:

providing a first transistor coupled with the first pair of current mirrored transistors and a pre-charge voltage and a second transistor coupled with the second pair of current mirrored transistors and the pre-charge voltage; and

providing a pre-charge circuit coupled between inputs of the first pair of current mirrored transistors and the second pair of current mirrored transistors.

23. The method of claim 22 wherein the first stage further includes an additional transistor between the inputs of the first pair of current mirrored transistors and the second pair of current mirrored transistors.

24. The method of claim 17 wherein the first stage providing further includes:

providing a first transistor coupled to the first pair of current mirrored transistors;

providing a second transistor coupled to the second pair of current mirrored transistors; and

providing an enabling transistor coupled to the first transistor and the second transistor, the enabling transistor for selectively enabling the first stage and the second stage.

25. The method of claim 24 wherein the first stage providing further includes:

providing a first transistor coupled with the first pair of current mirrored transistors and a pre-charge voltage;

providing a second transistor coupled with the second pair of current mirrored transistors and the pre-charge voltage; and

providing a pre-charge circuit coupled between inputs of the first pair and the second pair.

26. The method of claim 25 wherein the first stage further includes an additional transistor between the inputs of the first pair of current mirrored transistors and the second pair of current mirrored transistors.

27. The providing of claim 17 wherein the second stage further includes a plurality of transistors configured as a differential voltage sense amplifier.

28. The method of claim 17 further comprising

providing at a plurality of source lines coupled to the plurality magnetic storage cells;

providing at least one write driver coupled to the plurality of bit lines and the plurality of source lines, the write driver including a plurality of logic gates configured to selectively couple at least one of the plurality of bit lines to a first high voltage and at least one of the plurality of source lines to a first low voltage and to selectively the at least one of the plurality of bit lines to a second low voltage and the at least one of the plurality of source lines to a second high voltage.

29. The method of claim 17 further comprising:

Configuring the plurality of bit lines and the at least one reference line to be selectively pre-charged to a pre-charge state before the sense amplifier is enabled.

30. The method of claim 29 wherein the pre-charge state is ground.

31. The method of claim 17 wherein the first stage includes a plurality of outputs, the method further comprising:

Providing a transistor coupled between the plurality of outputs, the transistor for equalizing the plurality of outputs prior to a read operation.

32. A method for providing a magnetic memory comprising:

providing a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic element and at least one selection device, the at least one magnetic element being programmable using at least one write current driven through the magnetic element;

providing a plurality of bit lines corresponding to the plurality of magnetic storage cells;

providing a plurality of source lines corresponding to the plurality of magnetic storage cells;

providing at least one reference line for providing at least one reference signal;

providing at least one sense amplifier coupled with the plurality of bit lines and the at least one reference line, the at least one sense amplifier having logic and a plurality of stages, the plurality of stages including a first stage and a second stage, the first stage for converting at least one current signal to at least one differential voltage signal and the second stage for amplifying the at least one differential voltage signal, the logic for selectively disabling at least one of the first stage and the second stage in the absence of a read operation and enabling the first stage and the second stage during the read operation, the logic including a plurality of transistor coupled between the first stage and the second stage and a plurality of transmission gates coupled between the first and second stages, the first stage including a first pair of current mirrored transistors and a second pair of current mirrored transistors coupled with the first pair of current mirrored transistors, the first pair of current mirrored transistors and the second pair of current mirrored transistors providing the at least one differential voltage signal, the first stage also including at least one of a resistor pair and a transistor pair, the resistor pair including a first resistor coupled to the first pair of current mirrored transistors and a second resistor coupled to the second pair of current mirrored transistors, the first stage also including an enabling transistor coupled to the first resistor and the second resistor, the enabling transistor for selectively enabling the first stage and the second stage, the transistor pair including a first transistor coupled to the first pair of current mirrored transistors and a second transistor, substantially identical to the first transistor, coupled to the second pair of current mirrored transistors, the first stage also including an enabling transistor coupled to the first transistor and the second transistor, the enabling transistor for selectively enabling the first stage and the second stage.