Method and Device for Reconstructing a Data Clock from Asynchronously Transmitted Data Packets

• US 20090041028A1
• Filed: 08/06/2007
• Published: 02/12/2009
• Est. Priority Date: 08/06/2007
• Status: Active Grant

• Current Assignee: Intel Germany GmbH (Intel Corporation)
• Original Assignee: Lantiq Deutschland GMBH (Intel Corporation)
• Inventors: Kramer, Ronalf
• Granted Patent: US 8,363,764 B2
• Time in Patent Office: Days
• US Class Current: 370/395.620
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

For reconstructing a data clock from asynchronously transmitted data packets, a control loop is provided which includes a controlled oscillator. An input signal of the control loop is generated on the basis of the received data packets. At least one high-pass type filter is provided in a signal path of the control loop. The data clock for the synchronous output of data is generated on the basis of an output signal of the controlled oscillator.

Claims

1. A method of reconstructing a data clock from asynchronously transmitted data packets, the method comprising:

receiving data packets containing data to be synchronously output on the basis of a data clock;

providing a control loop with a controlled oscillator to generate the data clock;

generating an input signal of the control loop on the basis of the received data packets; and

providing at least one high-pass type filter in a signal path of the control loop.

2. The method according to claim 1, wherein the high-pass type filter comprises a first order filter.

3. The method according to claim 1, wherein the high-pass type filter has a transfer function of the type H(z)=1−

z<sup>−

1</sup>.

4. A method of reconstructing a data clock from asynchronously transmitted data packets, the method comprising:

receiving data packets containing data to be synchronously output on the basis of a data clock;

generating a data reception progress signal on the basis of the received data packets;

generating a data output progress signal on the basis of the data clock for the synchronous output of data;

high-pass type filtering the data reception progress signal;

high-pass type filtering the data output progress signal;

generating a difference signal on the basis of the filtered data reception progress signal and the filtered data output progress signal;

generating a control signal of a controlled oscillator on the basis of the difference signal; and

generating the data clock for the synchronous output of data on the basis of an output signal of the controlled oscillator.

5. The method according to claim 4, wherein the high-pass type filtering of the data reception progress signal and/or of the data output progress signal is accomplished by a first order filter.

6. The method according to claim 4, wherein the high-pass type filtering of the data reception progress signal and/or of the data output progress signal is accomplished with a filter transfer function of the type H(z)=1−

z<sup>−

1</sup>.

7. The method according to claim 4, wherein the high-pass type filtering of the data reception progress signal and/or of the data output progress signal comprises an overflow processing of the data reception progress signal and/or of the data output progress signal, respectively.

8. The method according to claim 4, further comprising:

extracting a sequence number from the received data packets so as to generate a sequence number signal;

high-pass type filtering of the sequence number signal; and

generating the difference signal on the further basis of the filtered sequence number signal.

9. The method according to claim 8, wherein the high-pass type filtering of the sequence number signal is accomplished by a first order filter.

10. The method according to claim 8, wherein the high-pass type filtering of the sequence number signal is accomplished with a filter transfer function of the type H(z)=1−

z<sup>−

1</sup>.

11. The method according to claim 8, wherein the high-pass type filtering of the sequence number signal comprises an overflow processing of the sequence number signal.

12. The method according to claim 8,

wherein the filtered data reception progress signal and the filtered sequence number signal are multiplied so as to obtain a product signal, and

wherein the difference signal is generated on the basis of the product signal.

13. The method according to claim 12,

wherein the product signal is accumulated over frames of multiple received data packets so as to obtain an accumulated product signal, and

wherein the difference signal is generated on the basis of the accumulated product signal.

14. A method of reconstructing a data clock from asynchronously transmitted data packets, the method comprising:

receiving data packets containing data to be synchronously output on the basis of a data clock;

extracting remote timestamps from the received data packets so as to obtain a first timestamp signal;

generating local timestamps on the basis of a local reference clock so as to obtain a second timestamp signal;

high-pass type filtering of the first timestamp signal;

high-pass type filtering of the second timestamp signal;

generating a difference signal on the basis of the filtered first timestamp signal and the filtered second timestamp signal;

generating a control signal of a controlled oscillator on the basis of the difference signal; and

generating the data clock for the synchronous output of data on the basis of an output signal of the controlled oscillator.

15. The method according to claim 14, wherein the high-pass type filtering of the first timestamp signal and/or of the second timestamp signal is accomplished by a first order filter.

16. The method according to claim 14, wherein the high-pass type filtering of the first timestamp signal and/or of the second timestamp signal is accomplished with a filter transfer function of the type H(z)=1−

z<sup>−

1</sup>.

17. The method according to claim 14, wherein the high-pass type filtering of the first timestamp signal and/or of the second timestamp signal comprises an overflow processing of the first timestamp signal or the second timestamp signal, respectively.

18. The method according to claim 14, further comprising:

buffering the received data packets in a buffer; and

controlling the size of the buffer by adding or deleting data packets,

wherein in case of adding or deleting a data packet, the value of the filtered first timestamp signal is replaced with a previous value of the filtered first timestamp signal.

19. The method according to claim 14, further comprising:

detecting a loss of a data packet; and

upon detection of a loss of a data packet, replacing a value of the filtered first timestamp signal with a previous value of the first timestamp signal.

20. A device for reconstructing a data clock from asynchronously transmitted data packets, the device comprising:

a control loop comprising a controlled oscillator, the control loop being configured to generate a data clock for the synchronous output of data received via asynchronously transmitted data packets; and

at least one high-pass type filter provided in a signal path of the control loop.

21. The device according to claim 20, wherein the at least one high-pass type filter comprises a first order filter.

22. The device according to claim 20, wherein the at least one high-pass type filter has a transfer function of the type H(z)=1−

z<sup>−

1</sup>.

23. A device for reconstructing a data clock from asynchronously transmitted data packets, the device comprising:

a first counter configured to generate a data reception progress signal on the basis of received data packets containing data to be synchronously output on the basis of a data clock;

a controlled oscillator, the data clock being derivable from an output signal of the controlled oscillator;

a second counter configured to generate a data output progress signal on the basis of the data clock;

a first high-pass type filter configured to receive the data reception progress signal and to output a filtered data reception progress signal;

a second high-pass type filter configured to receive the data output progress signal and to output a filtered data output progress signal; and

a combination stage configured to generate a difference signal on the basis of the filtered data reception progress signal and the filtered data output progress signal,

wherein a control signal of the controlled oscillator is generated on the basis of the difference signal.

24. The device according to claim 23, wherein the first high-pass type filter and/or the second high-pass type filter comprises a first order filter.

25. The device according to claim 23, wherein the first high-pass type filter and/or the second high-pass type filter has a transfer function of the type H(z)=1−

z<sup>−

1</sup>.

26. The device according to claim 23, wherein the first high-pass type filter and/or the second high-pass type filter is configured to accomplish an overflow processing of the data reception progress signal or the data output progress signal, respectively.

27. The device according to claim 23, further comprising:

an extraction stage configured to extract a sequence number from the received data packets and to generate a corresponding sequence number signal; and

a third high-pass type filter configured to receive the sequence number signal and to output a filtered sequence number signal,

wherein the combination stage is configured to generate the difference signal on the further basis of the filtered sequence number signal.

28. The device according to claim 27, wherein the third high-pass type filter comprises a first order filter.

29. The device according to claim 27, wherein the third high-pass type filter has a transfer function of the type H(z)=1−

z<sup>−

1</sup>.

30. The device according to claim 27, wherein the third high-pass type filter is configured to accomplish an overflow processing of the sequence number signal.

31. The device according to claim 30, further comprising:

a multiplication stage configured to receive the filtered data reception progress signal and the filtered sequence number signal and to output a product signal,

wherein the combination stage is configured to generate the difference signal on the basis of the product signal.

32. The device according to claim 31, further comprising:

an accumulator stage configured to accumulate the product signal over multiple received data packets and to output an accumulated product signal,

wherein the combination stage is configured to generate the difference signal on the basis of the accumulated product signal.

33. A device for reconstructing a data clock from asynchronously transmitted data packets, the device comprising:

an extraction stage configured to extract remote timestamps from received data packets containing data to be synchronously output on the basis of a data clock, and to output a first timestamp signal;

a controlled oscillator, the data clock being generated on the basis of an output signal of the controlled oscillator;

a local timestamp generator configured to generate local timestamps on the basis of a local reference clock signal so as to obtain a second timestamp signal;

a first high-pass type filter configured to receive the first timestamp signal;

a second high-pass type filter configured to receive the second timestamp signal; and

a combination stage configured to generate a difference signal on the basis of the filtered first timestamp signal and the filtered second timestamp signal,

wherein a control signal of the controlled oscillator is generated on the basis of the difference signal.

34. The device according to claim 33, wherein the first high-pass type filter and/or the second high-pass type filter comprises a first order filter.

35. The device according to claim 33, wherein the first high-pass type filter and/or the second high-pass type filter has a transfer function of the type H(z)=1−

z<sup>−

1</sup>.

36. The device according to claim 33, wherein the first high-pass type filter and/or the second high-pass type filter is configured to accomplish an overflow processing of the first timestamp signal or of the second timestamp signal, respectively.

37. The device according to claim 33, further comprising:

a buffer configured to buffer the received data packets; and

a control stage configured to control the size of the buffer by adding or deleting data packets and to generate an indication signal in case of adding or deleting a data packet,

wherein the first high-pass type filter is configured to replace the value of the filtered first timestamp signal with a previous value of the filtered first timestamp signal on the basis of the indication signal.

38. The device according to claim 33, further comprising a packet loss detector configured to detect a loss of a data packet and to generate an indication signal in case of a loss of a data packet, wherein the first high-pass type filter is configured to replace the value of the filtered first timestamp signal with a previous value of the filtered first timestamp signal on the basis of the indication signal.