Structure and Method for Surfaced-Passivated Zinc-Oxide

• US 20090042333A1
• Filed: 08/27/2008
• Published: 02/12/2009
• Est. Priority Date: 12/20/2005
• Status: Active Grant

• Current Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Kiesel, Peter, Schmidt, Oliver, Van de Walle, Christian G.
• Granted Patent: US 7,745,272 B2
• Time in Patent Office: Days
• US Class Current: 438/85
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: H01L 29/225 in different semiconductor regions , e.g. heterojunctions

Abstract

A semiconductor device has a heterostructure including a first layer of semiconductor oxide material. A second layer of semiconductor oxide material is formed on the first layer of semiconductor oxide material such that a two dimensional electron gas builds up at an interface between the first and second materials. A passivation layer on the outer surface stabilizes the structure. The device also has a source contact and a drain contact.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

providing a first and second layers of semiconductor oxide material such that a two dimensional electron gas will form at an interface between the first and second layers;

forming a passivation layer on an outer surface of a structure formed of the first and second layers; and

depositing source and drain contacts on the passivation layer.

2. The method of claim 1, providing a substrate further comprising providing a substrate from the group consisting of:

silicon, sapphire, zinc oxide, cadmium, silicon carbide, SCAM and gallium nitride.

3. The method of claim 1, providing the first and second layers further comprising providing a layer of zinc oxide.

4. The method of claim 1, providing the first and second layers further comprising providing a layer of a zinc oxide alloy.

5. The method of claim 1, the method further comprising growing a third layer of semiconductor oxide material on the second layer to form the outer surface of the structure.

6. The method of claim 1, the method further comprising depositing a metal gate in a region between the source contact and the drain contact.

7. The method of claim 1, forming a passivation layer further comprising forming a layer of one of the group consisting of:

silicon, silicon oxide, silicon nitride, silicon oxynitride.

8. The method of claim 1, forming a passivation layer further comprising forming one selected from the group consisting of:

a thin layer deposited in-situ after growth of the semiconductor oxide, an organic compound, polyimide and a self-assembled monolayer.

9. The method of claim 1, forming a passivation layer further comprising forming a passivation layer such that a surface conductivity is one of either avoided or destroyed.