METHOD AND STRUCTURE USING SELECTED IMPLANT ANGLES USING A LINEAR ACCELERATOR PROCESS FOR MANUFACTURE OF FREE STANDING FILMS OF MATERIALS

• US 20090042369A1
• Filed: 01/25/2008
• Published: 02/12/2009
• Est. Priority Date: 01/29/2007
• Status: Active Grant

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J.
• Granted Patent: US 7,910,458 B2
• Time in Patent Office: Days
• US Class Current: 438/463
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/26593 at a temperature lower than room temperature

Abstract

A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles provided at a first implant angle generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature. In a specific embodiment, the method includes subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles at a second implant angle generated using the linear accelerator, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature, which is higher than the first temperature. The method frees the thickness of detachable material using a cleaving process, e.g., controlled cleaving process.

Claims

1. A method for fabricating free standing thickness of materials using one or more semiconductor substrates, comprising:

providing a semiconductor substrate having a surface region and a thickness;

subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to define a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature, the first plurality of high energy particles being provided at a first implant angle;

subjecting the semiconductor substrate to a treatment process;

subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles generated using the linear accelerator, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level, the semiconductor substrate being maintained at a second temperature, the second plurality of particles being provided at a second implant angle; and

freeing the thickness of detachable material using a cleaving process.

2. The method of claim 1 wherein the semiconductor substrate comprises monocrystalline silicon.

3. The method of claim 1 wherein the semiconductor substrate comprises polysilicon silicon.

4. The method of claim 1 wherein the first high energy particles comprise hydrogen species.

5. The method of claim 4 wherein the hydrogen species are provided at a dose of 2×

10¹⁶ per cm² and less.

6. The method of claim 4 wherein the hydrogen species are provided at a dose of 5×

10¹⁵ per cm² and less.

7. The method of claim 1 wherein the first high energy particles comprise helium species.

8. The method of claim 1 wherein the semiconductor substrate is provided on a tray device.

9. The method of claim 8 wherein the tray device provides for the first implant angle and the second implant.

10. The method of claim 1 wherein the first implant angle is about zero to about 30 degrees.

11. The method of claim 1 wherein the first implant angle is about zero to about 25 degree.

12. The method of claim 1 wherein the second high energy particles comprises hydrogen species.

13. The method of claim 12 wherein the hydrogen species comprise a dose of 5×

10¹⁶ per cm² and less.

14. The method of claim 12 wherein the hydrogen species comprise a dose 5×

10¹⁵ per cm² and less.

15. The method of claim 1 wherein the second high energy particles comprises helium species or a combination of helium species and hydrogen species originated in a remote plasma system.

16. The method of claim 1 wherein the second implant angle is about zero to about 15 degree.

17. The method of claim 1 wherein the second implant angle is about zero to about seven degree.

18. The method of claim 1 wherein the linear accelerator comprises a radio frequency quadrupole (RFQ).

19. The method of claim 1 wherein the linear accelerator comprises a drift tube linear accelerator (DTL).

20. The method of claim 1 wherein the linear accelerator comprises a RF-Focused Interdigitated linear accelerator (RFI).

21. The method of claim 1 wherein the first plurality of high energy particles are provided in an energy ranging from 1 MeV to 5 MeV.

22. The method of claim 1 wherein the gettering sites comprise a microscopic defect region within a vicinity of the cleave region.

23. The method of claim 1 wherein the microscopic defect region comprises a plurality of voids provided between certain crystal planes of the semiconductor substrate.

24. The method of claim 1 wherein the treatment process is a thermal process provided at a temperature of 400 Degree Celsius or higher to render the microscopic defect region to be close to the cleave region and stabilize the microscopic defect region.

25. The method of claim 1 wherein the first temperature ranges from about −

100 Degree Celsius to about 250 Degree Celsius.

26. The method of claim 1 wherein the first temperature is less than about 250 Degree Celsius.

27. The method of claim 1 wherein the second temperature is greater than about 250 Degree Celsius and no greater than 550 Degrees Celsius.

28. The method of claim 1 wherein the thickness of detachable material has a thickness greater than about 50 um.

29. The method of claim 1 wherein the thickness of detachable material has a thickness greater than about 80 um.

30. The method of claim 1 wherein the thickness of detachable material has a thickness greater than about 100 um.

31. The method of claim 1 wherein the cleaving process is a controlled cleaving process.

32. The method of claim 1 wherein the cleaving process is a thermal process.

33. The method of claim 1 wherein the second temperature ranges from about 20 Degree Celsius to about 450 Degree Celsius.

34. The method of claim 1 wherein the first plurality of high energy particles and the second plurality of high energy particles are provided in an expanded beam from the linear accelerator.

35. The method of claim 34 wherein the expanded beam has a dimension of about 500 mm in diameter on the surface region of the semiconductor substrate.

36. The method of claim 1 wherein the linear accelerator comprises a DC accelerator.

37. A method for forming a free standing thickness of layer transferred material, the method comprising:

providing a crystalline substrate material having a surface region;

introducing a plurality of first particles at a first angle at a first dose range and within a first temperature range, whereupon the first dose range being less than an amount sufficient to cause the plurality of particles to be permanently disposed in the crystalline substrate material at an accumulation region, through the surface region to the accumulation region of the crystalline substrate material to form an implant profile having a peak concentration and a base spatially disposed within a dimension to form the accumulation region, the first particles causing a plurality of defects in the crystalline material in the accumulation region, the accumulation region being defined by a depth greater than about 20 microns beneath the surface region and a slice of crystalline material to be detached between the accumulation region and the surface region;

performing a treatment process on the crystalline substrate material to cause formation of a plurality of substantially permanent defects that have been quenched in the crystalline substrate material from the first particles in the accumulation region; and

introducing a plurality of second particles at a second angle at a second dose range and a second temperature range into the accumulation region to increase an internal stress in the accumulation region to cause a portion of the accumulation region to be cleavable; and

forming a free standing thickness of crystalline material by detaching the thickness of crystalline material from a remaining portion of the crystalline substrate material.

38. The method of claim 37 wherein the crystalline substrate material is a single crystal silicon.

39. The method of claim 37 wherein the crystalline substrate material is a polycrystalline silicon.

40. The method of claim 37 wherein the crystalline substrate material is a silicon ingot, e.g., silicon boule.

41. The method of claim 37 wherein the plurality of first particles in the accumulation region are in a metastable state before the treatment process.

42. The method of claim 37 wherein the first dose range is from about 2×

10¹⁵ to 2×

10¹⁶ cm<sup>−

2</sup>.

43. The method of claim 37 wherein the plurality of first particles are introduced while the crystalline substrate material is maintained at a temperature ranging from about −

50 to 100 Degrees Celsius.

44. The method of claim 37 wherein the plurality of first particles are introduced while the crystalline substrate material is maintained at a temperature ranging from about −

100 to +250 Degrees Celsius.

45. The method of claim 37 wherein the first temperature and first dose causes a partially amorphized region within the accumulation region.

46. The method of claim 37 wherein the first temperature is less than about 200 Degrees Celsius.

47. The method of claim 37 wherein the treatment process comprises a thermal treatment process.

48. The method of claim 47 wherein the thermal treatment process is a thermal anneal step to develop a permanent defect network in the accumulation region.

49. The method of claim 37 wherein the first plurality of particles are provided by a first beam.

50. The method of claim 37 wherein the crystalline substrate material is provided on a tray device.

51. The method of claim 50 wherein the tray device provides for the first angle and the second angle.

52. The method of claim 37 wherein the first angle is about zero to about 30 degrees.

53. The method of claim 37 wherein the first angle is about zero to about 25 degrees.

54. The method of claim 37 wherein the first plurality of particles comprises of hydrogen.

55. The method of claim 37 wherein the second plurality of particles are provided by a second beam.

56. The method of claim 37 wherein the second angle is about zero to about 15 degrees.

57. The method of claim 37 wherein the second angle is about zero to about seven degrees.

58. The method of claim 37 wherein the first plurality of particles and the second plurality of particles comprise same particles.

59. The method of claim 37 wherein the first temperature is ramped to the second temperature.

60. The method of claim 37 wherein the second dose is provided in a continuous manner after the first dose.

61. The method of claim 37 wherein the second dose is provided after the first dose.

62. The method of claim 37 wherein the first dose rate is provided at 500 microamperes to 50 milliamperes and a total dose rate is calculated by integrating an implantation flux rate over the expanded beam area.

63. The method of claim 37 wherein the surface region is substantially flat after the second dose.

64. The method of claim 37 wherein the base has a width of about 2 Rp and less.

65. The method of claim 37 wherein the second plurality of particles are provided by subjecting the surface region to a hydrogen bearing environment.

66. The method of claim 65 wherein the second plurality of particles are provided while the thickness of material is held at a second temperature range selected to be sufficient to allow diffusion and accumulation of the plurality of particles within the accumulation region defined by the first plurality of particles.

67. The method of claim 65 wherein the hydrogen bearing environment is selected from a hydrogen plasma, a hydrogen atmosphere, or hydrogen-rich spin-on materials, or a hydrogen ion rich liquid such as an acid.

68. A method for fabricating free standing thickness of materials using one or more semiconductor substrates, comprising:

providing a semiconductor substrate having a surface region and a thickness;

subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a patterned region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to define a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature, the first plurality of high energy particles being provided at a first implant angle, the patterned region being provided to cause initiation of a cleaving action;

subjecting the semiconductor substrate to a treatment process;

subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level, the semiconductor substrate being maintained at a second temperature, the second plurality of particles being provided at a second implant angle;

initiating the cleaving action at a selected region of the patterned region to detach a portion of the thickness of detachable material using a cleaving process; and

freeing the thickness of detachable material using a cleaving process.

69. The method of claim 68 wherein the patterned region is provided in a peripheral region of the semiconductor substrate.

70. The method of claim 68 wherein the patterned region is provided in a z-direction from the surface region to the gettering sites.

71. The method of claim 68 wherein the patterned region is provided within the gettering sites.

72. A method for forming a film of material from a bulk semiconductor substrate, the method comprising:

providing a semiconductor substrate having a surface region and a thickness;

subjecting the surface region of the semiconductor substrate to a plurality of particles to form a cleave region, the cleave region being defined underlying the surface region to form a stressed region and to define a thickness of material to be detached, the thickness of material having a thickness of about 20 microns and greater;

freeing the thickness of detachable material using a cleaving process while maintaining a portion of the stress region attached to the thickness of material to cause the thickness of material to be characterized by a deformed shape; and

removing the portion of the stress region attached to the thickness of material to cause the deformed shape to be removed and yield a substantially planar shape.

73. The method of claim 72 wherein the stressed region comprises the plurality of particles embedded therein.

74. The method of claim 72 wherein the removing comprises etching the portion of the stressed region.

75. The method of claim 72 wherein the removing comprises thermally treating the detached thickness of material to relax the stressed region.

76. The method of claim 72 wherein the detached thickness of material comprises single crystal silicon or polysilicon.

77. The method of claim 72 wherein the semiconductor substrate is square-like in shape.

78. The method of claim 77 wherein the deformed shape comprises a first curled edge region opposite a second curled edge region and an axis in between the first curled edge region and the second curled edge region, the axis connecting a third edge region opposite of a fourth edge region.

79. The method of claim 78 wherein the forming of the cleave region comprising:

subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a patterned region of a plurality of gettering sites within a cleave region, the semiconductor substrate being maintained at a first temperature, the first plurality of high energy particles being provided at a first implant angle;

subjecting the semiconductor substrate to a treatment process;

subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level, the semiconductor substrate being maintained at a second temperature, the second plurality of particles being provided at a second implant angle.

80. A method for forming a film of material from a bulk semiconductor substrate, the method comprising:

providing a semiconductor substrate having a surface region and a thickness;

subjecting the surface region of the semiconductor substrate to a plurality of particles to form a cleave region, the cleave region being defined underlying the surface region to form a stressed region and to define a thickness of material to be detached, the thickness of material having a thickness of about 20 microns and greater;

initiating a separation of a portion of the thickness of material to be detached at an edge region of the cleave region using a selective energy placement at a spatial region within a vicinity of the cleave region to form a detached portion of the thickness of material having a portion of the stressed region; and

bending away the detached portion of the thickness of material from the spatial region and causing a deformed shape in the thickness of material to be detach to facilitate removal of the thickness of material from a remaining substrate portion.

81. The method of claim 80 wherein the energy is selected from a light source, a laser source, a thermal source, a radiation source, a mechanical source, a chemical source, a gravitational source, or a fluid source.

82. A method for fabricating free standing thickness of materials using one or more semiconductor substrates, comprising:

providing a semiconductor substrate having a surface region and a thickness;

subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles comprising D+ species generated using a linear accelerator to form a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to define a thickness of material to be detached;

subjecting the semiconductor substrate to a treatment process;

subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles comprising H2+ species using the linear accelerator, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level;

initiating the cleaving action at a selected region of the cleave region to detach a portion of the thickness of detachable material using a cleaving process; and

freeing the thickness of detachable material.