Methods and apparatus for calibration of automatic gain control in broadcast tuners

• US 20090042526A1
• Filed: 08/08/2007
• Published: 02/12/2009
• Est. Priority Date: 08/08/2007
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Rose, Steven, Abaskharoun, Nazmy, L'Bahy, Hassan, Maulik, Prabir C., Paterson, Donald
• Granted Patent: US 7,853,229 B2
• Time in Patent Office: Days
• US Class Current: 455/234.100
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals

Abstract

In one aspect, a calibration component configured to calibrate an automatic gain controller (AGC) for use in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing is provided. The calibration component comprises a calibration signal generator implemented on the RF integrated circuit, the calibration signal generator adapted to generate a generally known calibration signal, a power detector implemented on the RF integrated circuit and configured to detect, during calibration, at least one power characteristic of the calibration signal and to provide a power level signal indicative of the at least one detected power characteristic, a gain controller implemented on the digital integrated circuit, the gain controller adapted to generate at least one error signal based, at least in part, on a comparison between the power level signal provided by the power detector and a first reference signal, an offset signal generator implemented on the RF integrated circuit and configured to generate an offset signal based, at least in part, on the at least one error signal and a summing element implemented on the RF integrated circuit and adapted to combine the offset signal with the power level signal provided by the power detector to provide an adjusted power level signal.

Claims

1. A calibration component configured to calibrate an automatic gain controller (AGC) for use in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing, the calibration component comprising:

a calibration signal generator implemented on the RF integrated circuit, the calibration signal generator adapted to generate a generally known calibration signal;

a power detector implemented on the RF integrated circuit and configured to detect, during calibration, at least one power characteristic of the calibration signal and to provide a power level signal indicative of the at least one detected power characteristic;

a gain controller implemented on the digital integrated circuit, the gain controller adapted to generate at least one error signal based, at least in part, on a comparison between the power level signal provided by the power detector and a first reference signal;

an offset signal generator implemented on the RF integrated circuit and configured to generate an offset signal based, at least in part, on the at least one error signal; and

a summing element implemented on the RF integrated circuit and adapted to combine the offset signal with the power level signal provided by the power detector to provide an adjusted power level signal.

2. The calibration component of claim 1, wherein the calibration signal generator includes an oscillator.

3. The calibration component of claim 2, wherein the calibration signal generator includes a ring oscillator

4. The calibration component of claim 1, wherein components of the calibration component form a control loop adapted to drive the at least one error signal to zero or substantially zero, the calibration component completing operation when the control loop has substantially converged.

5. The calibration component of claim 4, wherein the offset signal generator includes a digital-to-analog converter (DAC) configured to generate the offset signal from the DAC code representing a digital number that is modified during calibration based, at least in part, on the at least one error signal.

6. The calibration component of claim 5, wherein the offset signal generator includes a storage element to store a final DAC code for generating the offset signal when the control loop has converged.

7. The calibration component of claim 6, wherein the offset signal generator includes a finite state machine (FSM) adapted to modify the DAC code based, at least in part, on the at least one error signal.

8. The calibration component of claim 1, further comprising an analog-to-digital converter (ADC) arranged between the power detector and the gain controller to convert the power level signal to a digital power level signal for digital processing by the gain controller.

9. The calibration component of claim 8, wherein the ADC is implemented on the digital integrated circuit.

10. The calibration component of claim 8, wherein the ADC is implemented on the RF integrated circuit.

11. The calibration component of claim 8, wherein the gain controller includes a summation element to generate a first error signal based on a difference between the reference signal and the digital power level signal.

12. The calibration component of claim 11, wherein the gain controller includes a integrator to integrate the first error signal to provide an integrated error signal.

13. The calibration component of claim 6 in combination with the AGC, the AGC comprising:

a variable gain amplifier (VGA) implemented on the RF integrated circuit, the VGA adapted to receive the broadcast signal and to apply a variable gain to the broadcast signal based, at least in part, on a gain signal to provide an amplified broadcast signal;

the power detector configured, after calibration, to detect at least one power characteristic of the amplified broadcast signal and to provide a power level signal indicative of the at least one detected power characteristics;

the summing element configured to combine the offset signal generated from the final DAC code to provide the adjusted power level signal; and

the gain controller adapted to generate at least one error signal based, at least in part, on a comparison between the adjusted power level signal provided by the power detector and a second reference signal, wherein the gain signal is based, at least in part, on the at least one error signal generated by the gain controller.

14. The combination of claim 13, further comprising a gain mapper configured to map the integrated error signal to the gain signal.

15. The combination of claim 14, wherein the gain mapper is implemented on the RF integrated circuit.

16. The combination of claim 14, wherein the gain mapper is implemented on the digital integrated circuit.

17. The combination of claim 16, wherein the first reference signal and the second reference signal are the same.

18. An automatic gain controller (AGC) for use in a tuner adapted to isolate a selected channel from a multi-channel broadcast signal, the AGC configured to operate in a calibration mode adapted to calibrate the AGC, and an operation mode adapted to apply a variable gain to a broadcast signal, the AGC comprising:

a first control loop comprising;

a calibration signal generator adapted to generate a calibration signal;

a power detector configured to detect at least one power characteristic of a received input signal and to provide a power level signal indicative of the at least one detected power characteristic;

a summing element to combine the power level signal with an offset signal to provide an adjusted power level signal;

a gain controller including a reference signal, the gain controller adapted to generate at least one error signal indicative of a difference between the reference signal and the adjusted power level signal; and

an offset signal generator adapted to provide the offset signal to the summing element, the offset signal generator configured to adjust the offset signal during the calibration mode based, at least in part, on the at least one error signal; and

a second control loop comprising;

a variable gain amplifier (VGA) adapted to receive the broadcast signal and to apply a variable gain to the broadcast signal based on a gain signal to provide an amplified broadcast signal;

the power detector;

the summing element; and

the gain controller,

wherein, in the calibration mode, the first control loop is operational and the received input signal to the power detector is the calibration signal, the first control loop operating to modify the offset signal such that it reflects an offset error of the AGC, and wherein, in the operation mode, the second control loop is operational and the received input signal to the power detector is the amplified broadcast signal, the second control loop operating to maintain a power level of the amplified broadcast signal within a desired range.

19. The AGC of claim 18, wherein the AGC is adapted for use with a tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing, and wherein the VGA, the calibration signal generator, the power detector and the offset signal generator are implemented on the RF integrated circuit, and wherein the gain controller is implemented on the digital integrated circuit.

20. The AGC of claim 18, wherein the offset signal generator comprises:

a state machine configured to map the error signal into a digital-to-analog converter (DAC) code indicating the value of the offset signal; and

a DAC configured to convert the DAC code into the offset signal.

21. The AGC of claim 18, further comprising a multiplexer arranged to receive the calibration signal and the amplified broadcast signal, the multiplexer adapted to provide the calibration signal to the power detector when in the calibration mode and to provide the amplified broadcast signal to the power detector when in the operation mode.

22. The AGC of claim 21, wherein the AGC is automatically set to the calibration mode upon power-up of the AGC.

23. The AGC of claim 22, wherein the AGC is in operation mode after the calibration process is completed.

24. The AGC of claim 21, wherein the gain controller includes a integrator to integrate the first error signal to provide an integrated error signal.

25. The AGC of claim 24, further comprising a gain mapper configured to map the integrated error signal to the gain signal.

26. The AGC of claim 25, wherein the gain mapper is implemented on the RF integrated circuit.

27. The AGC of claim 25, wherein the gain mapper is implemented on the digital integrated circuit.

28. A method of calibrating an automatic gain controller (AGC) for use in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing, the method comprising:

generating, on the RF integrated circuit, a generally known calibration signal;

detecting, on the RF integrated circuit, at least one power characteristic of the calibration signal;

providing, on the RF integrated circuit, a first power level signal indicative of the at least one power characteristic of the calibration signal;

receiving, on the digital integrated circuit, the first power level signal;

generating, on the digital integrated circuit, a first error signal based, at least in part, on a comparison between the first power level signal and a first reference signal; and

generating an offset signal based, at least in part, on the first error signal; and

combining the offset signal with the first power level signal provided by the power detector to provide an adjusted first power level signal.

29. The method of claim 28, wherein generating the calibration signal includes generating the generally known calibration signal using an oscillator

30. The method of claim 29, wherein generating the calibration signal includes generating the generally known calibration signal using a ring oscillator.

31. The method of claim 28, wherein acts in the calibration method are repeated on the adjusted first power level signal until the first error signal is zero or substantially zero, or is determined to be sufficiently small, thereby indicating that the calibration is completed.

32. The method of claim 31, wherein a representation of the offset signal generated when the calibration is completed is stored for use in compensating for at least an offset error during operation of the AGC.

33. The method of claim 28, further comprising converting the adjusted first power level signal to a first digital power level signal for digital processing on the digital integrated circuit.

34. The method of claim 33, wherein converting the first power level signal is performed on the digital integrated circuit.

35. The method of claim 33, wherein converting the first power level signal is performed on the RF integrated circuit.

36. The method of claim 33, wherein generating the first error signal includes determining a difference between the reference signal and the first digital power level signal.

37. The method of claim 28, further comprising operating the AGC subsequent to completing calibration, operating the AGC comprising:

applying, on the RF integrated circuit, a variable gain to the broadcast signal based, at least in part, on a gain signal to provide an amplified broadcast signal;

detecting, on the RF integrated circuit, at least one power characteristic of the amplified broadcast signal;

providing, on the RF integrated circuit, a second power level signal indicative of the at least one power characteristic;

adjusting the second power level signal according to the stored offset signal to provide an adjusted second power level signal;

receiving, on the digital integrated circuit, the adjusted second power level signal;

generating, on the digital integrated circuit, a second error signal based, at least in part, on a comparison between the adjusted second power level signal and a reference signal; and

providing, on the RF integrated circuit, the gain signal based, at least in part, on the second error signal.