PROGRAMMING SCHEMES FOR MULTI-LEVEL ANALOG MEMORY CELLS

• US 20090043951A1
• Filed: 08/06/2008
• Published: 02/12/2009
• Est. Priority Date: 08/06/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Kasorla, Yoav, Shalvi, Ofir, Sokolov, Dotan, Sommer, Naftali
• Granted Patent: US 8,259,497 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence

Abstract

A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

Claims

1. A method for data storage, comprising:

storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels;

storing second data bits in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits; and

selecting a storage strategy responsively to a difference between the first and second times, wherein the storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

2. The method according to claim 1, wherein selecting the storage strategy is performed at the first time following storage of the first data bits.

3. The method according to claim 2, wherein selecting the storage strategy comprises drawing an inference with respect to the time difference based on a status of the memory cells following the storage of the first data bits.

4. The method according to claim 3, wherein drawing the inference comprises detecting that the set of the memory cells is partially-programmed following the storage of the first data bits.

5. The method according to claim 1, wherein selecting the storage strategy is performed at the second time.

6. The method according to claim 1, and comprising reading from the memory cells at least one set of the stored data bits, selected from among the first data bits and the second data bits, wherein the storage strategy is applied in reading the at least one set of data bits.

7. The method according to claim 6, wherein selecting the storage strategy comprises determining read thresholds to be used in reading the at least one set of data bits.

8. The method according to claim 6, wherein selecting the storage strategy comprises selecting a decoding process for reading the at least one set of data bits.

9. The method according to claim 1, wherein selecting the storage strategy comprises modifying a programming parameter used in storing the at least one group of the data bits.

10. The method according to claim 1, wherein storing the first and second data bits comprises applying to the memory cells a sequence of programming pulses that incrementally increase by a step size, and wherein selecting the storage strategy comprises modifying the step size.

11. The method according to claim 1, wherein storing the first and second data bits comprises encoding the at least one group of the data bits with an Error Correction Code (ECC), and wherein selecting the storage strategy comprises modifying a redundancy level of the ECC.

12. The method according to claim 1, wherein programming the memory cells to assume the first and second programming levels comprises writing to the cells predefined storage values that correspond to the respective programming levels and are separated from one another by predefined separations, and wherein selecting the storage strategy comprises modifying a separation between at least two programming levels selected from among the first and second programming levels.

13. The method according to claim 1, wherein selecting the storage strategy comprises measuring the difference between the first and second times and comparing the measured difference to a threshold.

14. The method according to claim 1, wherein storing the second data bits comprises retrieving the stored first data bits from the memory cells, caching the retrieved first data bits in a buffer and computing the second programming levels based on the cached first data bits and the second data bits, and wherein selecting the storage strategy comprises correcting errors in the cached first data bits and re-writing the first data bits, after correction of the errors, to the buffer prior to computing the second programming levels.

15. The method according to claim 1, wherein storing the second data bits comprises retrieving the stored first data bits from the memory cells, caching the retrieved first data bits in a buffer and computing the second programming levels based on the cached first data bits and the second data bits, and wherein selecting the storage strategy comprises:

correcting errors in the cached first data bits to produce error-corrected bits;

re-retrieving the first data bits from the memory cells after storage of the second data bits; and

selecting the storage strategy responsively to a discrepancy between the error-corrected bits and the re-retrieved first data bits.

16. The method according to claim 1, wherein selecting the storage strategy comprises:

retrieving at least part of the stored first data bits from the memory cells using one or more read thresholds;

processing the retrieved first data bits so as to modify the read thresholds;

re-retrieving the first data bits from the memory cells using the modified read thresholds; and

computing the second programming levels responsively to the second data bits and the re-retrieved first data bits.

17. The method according to claim 16, wherein processing the retrieved first data bits comprises detecting errors in the retrieved first data bits and modifying the read thresholds responsively to the detected errors.

18. A method for data storage, comprising:

storing first data bits in a memory device, which comprises a first set of multi-bit analog memory cells and a second set of digital memory cells, by programming the analog memory cells to assume respective first programming levels;

caching the first data bits in the digital memory cells;

accepting second data bits for storage in the first set of analog memory cells;

processing the accepted second data bits and the cached first data bits so as to compute respective second programming levels for the analog memory cells; and

storing the second data bits in the first set of analog memory cells by programming the analog memory cells to assume the respective second programming levels.

19. The method according to claim 18, wherein caching the first data bits comprises evaluating a criterion with respect to the first data bits, and caching the first data bits only responsively to meeting the criterion.

20. The method according to claim 19, and comprising, when the first data bits are not cached in the digital memory cells, retrieving the first data bits from the analog memory cells, correcting errors in the retrieved first data bits to produce error-corrected bits, and computing the second programming levels responsively to the second data bits and the error-corrected bits.

21. The method according to claim 20, wherein correcting the errors comprises detecting the errors by error detection circuitry in the memory device and correcting the errors by error correction circuitry external to the memory device responsively to detecting the errors.

22. The method according to claim 18, wherein storing the first data bits comprises applying to the analog memory cells a first sequence of programming pulses that incrementally increase by a first step size, and wherein storing the second data bits comprises applying to the analog memory cells a second sequence of the programming pulses that incrementally increase by a second step size, smaller than the first step size.

23. Apparatus for data storage, comprising:

programming circuitry, which is coupled to store first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels, and to store second data bits in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits; and

a processor, which is configured to select a storage strategy responsively to a difference between the first and second times, wherein the storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

24. The apparatus according to claim 23, wherein the processor is configured to select the storage strategy at the first time following storage of the first data bits.

25. The apparatus according to claim 24, wherein the processor is configured to select the storage strategy by drawing an inference with respect to the time difference based on a status of the memory cells following the storage of the first data bits.

26. The apparatus according to claim 25, wherein the processor is configured to draw the inference by detecting that the set of the memory cells is partially-programmed following the storage of the first data bits.

27. The apparatus according to claim 23, wherein the processor is configured to select the storage strategy at the second time.

28. The apparatus according to claim 23, and comprising reading circuitry, which is coupled to read from the memory cells at least one set of the stored data bits, selected from among the first data bits and the second data bits, wherein the processor is configured to apply the storage strategy in reading the at least one set of data bits.

29. The apparatus according to claim 28, wherein the processor is configured to select the storage strategy by determining read thresholds to be used in reading the at least one set of data bits.

30. The apparatus according to claim 28, wherein the processor is configured to select the storage strategy by selecting a decoding process for reading the at least one set of data bits.

31. The apparatus according to claim 23, wherein the processor is configured to select the storage strategy by modifying a programming parameter used in storing the at least one group of the data bits.

32. The apparatus according to claim 23, wherein the programming circuitry is coupled to store the first and second data bits by applying to the memory cells a sequence of programming pulses that incrementally increase by a step size, and wherein the processor is configured to select the storage strategy by modifying the step size.

33. The apparatus according to claim 23, wherein the processor is configured to encode the at least one group of the data bits with an Error Correction Code (ECC), and to select the storage strategy by modifying a redundancy level of the ECC.

34. The apparatus according to claim 23, wherein the programming circuitry is coupled to program the memory cells to assume the first and second programming levels by writing to the cells predefined storage values that correspond to the respective programming levels and are separated from one another by predefined separations, and wherein the processor is configured to select the storage strategy by modifying a separation between at least two programming levels selected from among the first and second programming levels.

35. The apparatus according to claim 23, wherein the processor is configured to select the storage strategy by measuring the difference between the first and second times and comparing the measured difference to a threshold.

36. The apparatus according to claim 23, and comprising reading circuitry, which comprises a buffer and is coupled to retrieve the stored first data bits from the memory cells, to cache the retrieved first data bits in the buffer and to compute the second programming levels based on the cached first data bits and the second data bits, wherein the processor is configured to correct errors in the cached first data bits and to re-write the first data bits, after correction of the errors, to the buffer prior to computing the second programming levels.

37. The apparatus according to claim 23, and comprising reading circuitry, which comprises a buffer and is coupled to retrieve the stored first data bits from the memory cells, to cache the retrieved first data bits in the buffer and to compute the second programming levels based on the cached first data bits and the second data bits, wherein the processor is configured to correct errors in the cached first data bits to produce error-corrected bits, to re-retrieve the first data bits from the memory cells after storage of the second data bits, and to select the storage strategy responsively to a discrepancy between the error-corrected bits and the re-retrieved first data bits.

38. The apparatus according to claim 23, and comprising reading circuitry, which is coupled to retrieve at least part of the stored first data bits from the memory cells using one or more read thresholds, wherein the processor is configured to process the retrieved first data bits so as to modify the read thresholds, to cause the reading circuitry to re-retrieve the first data bits from the memory cells using the modified read thresholds, and to compute the second programming levels responsively to the second data bits and the re-retrieved first data bits.

39. The apparatus according to claim 38, wherein the processor is configured to detect errors in the retrieved first data bits and to modify the read thresholds responsively to the detected errors.

40. A memory device, comprising:

a first set of multi-bit analog memory cells;

a second set of digital memory cells; and

control circuitry, which is coupled to store first data bits in the first set of analog memory cells by programming the analog memory cells to assume respective first programming levels, to cache the first data bits in the digital memory cells, to accept second data bits for storage in the first set of analog memory cells, to process the accepted second data bits and the cached first data bits so as to compute respective second programming levels for the analog memory cells, and to store the second data bits in the first set of analog memory cells by programming the analog memory cells to assume the respective second programming levels.

41. The memory device according to claim 40, and comprising a device package, wherein the analog memory cells, the digital memory cells and the control circuitry are packaged in the device package.

42. The memory device according to claim 40, wherein the control circuitry is coupled to evaluate a criterion with respect to the first data bits, and to cache the first data bits only responsively to meeting the criterion.

43. The memory device according to claim 42, wherein, when the first data bits are not cached in the digital memory cells, the control circuitry is coupled to retrieve the first data bits from the analog memory cells, to cause error correction circuitry external to the memory device to correct errors in the retrieved first data bits so as to produce error-corrected bits, and to compute the second programming levels responsively to the second data bits and the error-corrected bits.

44. The memory device according to claim 43, wherein the control circuitry comprises error detection circuitry, which is coupled to detect the errors, and wherein the control circuitry is coupled to cause the error correction circuitry to correct the errors responsively to detecting the errors by the error detection circuitry.

45. The memory device according to claim 40, wherein the control circuitry is coupled to store the first data bits by applying to the analog memory cells a first sequence of programming pulses that incrementally increase by a first step size, and to store the second data bits by applying to the analog memory cells a second sequence of the programming pulses that incrementally increase by a second step size, smaller than the first step size.

46. The memory device according to claim 40, wherein the digital memory cells comprise at least a first buffer for caching a currently-programmed memory page to be stored in the set of the analog memory cells, and a second buffer for caching at least one other memory page that was previously stored in the set of the analog memory cells.

47. The memory device according to claim 46, wherein the control circuitry is coupled to cache the second data bits in the first buffer and the first data bits in the second buffer.

48. The memory device according to claim 47, wherein the digital memory cells further comprise a third buffer for storing memory pages that were previously stored in the memory device, and wherein the control circuitry is coupled, responsively to accepting the second data bits, to copy the first data bits from the third buffer to the second buffer.

49. Apparatus for data storage, comprising:

a memory comprising a set of multi-bit analog memory cells;

programming circuitry, which is coupled to store first data bits in the set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels, and to store second data bits in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits; and

a processor, which is configured to select a storage strategy responsively to a difference between the first and second times, wherein the storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.