Semiconductor memory devices that are resistant to power attacks and methods of operating semiconductor memory devices that are resistant to power attacks
First Claim
1. A semiconductor memory device, comprising:
- a central processing unit configured to output an address through an address line and data through a data line;
a random converter coupled to the data line and configured to receive the data, to convert the data to randomized data, and to output the randomized data; and
a memory unit configured to receive the address through the address line and store the randomized data at the address;
wherein the random converter is configured to receive address information including a start address value and an end address value associated with the data, to generate and store a random number associated with each value from the start address value to the end address value of the address based on the address information, to perform a logical operation on the random number and data corresponding to the address to thereby generate the randomized data, and to output the randomized data.
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Accused Products
Abstract
A semiconductor memory device according to some embodiments includes a random converter that receives data and address information including a start address value and an end address value of the address from a central processing unit (CPU), generates and stores at least one random number for each address value from the start address value to the end address value, performs a logical operation on the random number and the data corresponding to the address, and responsively generates randomized data to be stored in memory. Accordingly, the semiconductor memory device randomizes a power consumption signature that can occur when data is stored, thereby writing and reading data in a manner that is resistant to a power attack.
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Citations
16 Claims
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1. A semiconductor memory device, comprising:
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a central processing unit configured to output an address through an address line and data through a data line; a random converter coupled to the data line and configured to receive the data, to convert the data to randomized data, and to output the randomized data; and a memory unit configured to receive the address through the address line and store the randomized data at the address; wherein the random converter is configured to receive address information including a start address value and an end address value associated with the data, to generate and store a random number associated with each value from the start address value to the end address value of the address based on the address information, to perform a logical operation on the random number and data corresponding to the address to thereby generate the randomized data, and to output the randomized data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of writing data in a memory device, comprising:
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outputting an address through an address line and data through a data line; generating randomized data in response to the data and the address by receiving address information including a start address value and an end address value, generating and storing at least one random number for each value from the start address value to the end address value of the address in response to the address information, and performing a logical operation on the random number and data corresponding to the address; and storing the randomized data at the address. - View Dependent Claims (12, 13, 14)
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15. A method of reading stored data in a semiconductor memory device, comprising:
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outputting randomized data corresponding to an address value received through an address line; and performing a logical operation on a random number corresponding to the address value and the randomized data to responsively generate original data, outputting the original data, and updating flag information; wherein the flag information indicates whether to store a new address and/or a new random number in a random number table in which the address value and the random number are stored, during a subsequent write operation of the semiconductor memory device. - View Dependent Claims (16)
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Specification