System and Method for Controlling Synchronous Functional Microprocessor Redundancy during Test and Analysis

• US 20090044057A1
• Filed: 08/09/2007
• Published: 02/12/2009
• Est. Priority Date: 08/09/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Choate, Michael L., Ryan, Arthur M., Ayers, Kevin E., Terrell, Douglas L.
• Granted Patent: US 7,873,874 B2
• Time in Patent Office: Days
• US Class Current: 714/40
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a under test (DUT) is coupled to both the gold processor and the TAP. Test signals are simultaneously provided to both the gold processor and the DUT such that the gold processor and the DUT operate in synchronous functional lockstep. The TAP may also input test signals into the gold processor and DUT simultaneously and access data from each of these processors through separate test data out (TDO) connections. Test output data accessed from the gold processor may be compared to test output data accessed from the DUT to determine if any differences are present. The comparison data generated may then be used for analysis purposes.

Claims

1. A system for testing a processor, the system comprising:

a gold processor;

a test access port (TAP) coupled to the gold processor and a processor that is a device under test (DUT), wherein the TAP is coupled to simultaneously provide a plurality test signals to both the gold processor and the DUT such that, during testing, the gold processor and the DUT operate in synchronous functional lockstep with respect to each other, wherein the TAP includes a first test data out (TDO) connection and a second TDO connection, wherein the first TDO connection is coupled to access test output data from the gold processor, and wherein the second TDO connection is coupled to access test output data from the DUT; and

an interface control unit coupled to the TAP, wherein the interface control unit is configured to cause the TAP to drive signals to both the gold processor and the DUT, and further configured to access test output data from the gold processor and the DUT independently of one another.

2. The system as recited in claim 1, wherein the TAP includes a plurality of test signal outputs each corresponding to one of the plurality of test signals, wherein each of the plurality of test signal outputs are shared by the gold processor and the DUT.

3. The system as recited in claim 2, wherein the plurality of test signal outputs is coupled to provide the plurality of test signals to the gold processor over a first plurality of signal paths, and wherein the plurality of test signal outputs is coupled to provide the plurality of test signals to the DUT over a second plurality of signal paths.

4. The system as recited in claim 3, wherein for a given one of the plurality of test signal outputs, a corresponding one of the first plurality of signal paths has a length substantially the same as a corresponding one of the second plurality of signal paths.

5. The system as recited in claim 4, wherein the length of the corresponding one of the first plurality signal paths is within 1/1000 of an inch of a length of the corresponding one of the second plurality of signal paths.

6. The system as recited in claim 3, wherein the system includes a comparator board having the first and second plurality of signal paths, wherein the TAP is mounted on the comparator board and wherein the comparator board further includes a first processor socket configured to receive the gold processor and a second processor socket configured to receive the DUT.

7. The system as recited in claim 6, wherein the system includes an interposer board and a system board, wherein the interposer board is coupled to the comparator board and further configured to be coupled to a third processor socket mounted on the system board.

8. The system as recited in claim 7, wherein the system board is configured to drive signals to the interface control unit to cause the TAP to provide test signals to the gold processor and the DUT, and wherein the system board is further coupled to receive test output data from the TAP via the interposer board.

9. The system as recited in claim 8, wherein the system includes a host computer having a display unit, and wherein the host computer is configured to output test results to the display unit.

10. The system as recited in claim 2, wherein the test signal outputs comprise outputs for:

a test clock signal;

a test mode select signal;

test data; and

a test reset signal.

11. The system as recited in claim 1, wherein the TAP is an IEEE 1149.1 test access port.

12. A method for testing a processor, the method comprising:

driving test signals from the TAP to a gold processor and a processor that is a under test (DUT), wherein the TAP is coupled to simultaneously provide a plurality test signals to both the gold processor and the DUT such that, during testing, the gold processor and the DUT operate in synchronous functional lockstep with respect to each other;

controlling the TAP with an interface control unit, wherein the interface control unit is configured to cause the TAP to perform said driving;

receiving test output data from the gold processor, wherein the test output data from the gold processor is received by the TAP through a first test data out (TDO) connection;

receiving test output data from the DUT, wherein the test output data from the DUT is receive by the TAP through a second TDO connection;

displaying test output data from the gold processor and test output data from the DUT; and

determining results of said testing.

13. The method as recited in claim 12 further comprising the TAP outputting test signals to the gold processor and the DUT from a plurality of shared test signal outputs.

14. The method as recited in claim 13, wherein the plurality of test signal outputs is coupled to provide the plurality of test signals to the gold processor over a first plurality of signal paths, and wherein the plurality of test signal outputs is coupled to provide the plurality of test signals to the DUT over a second plurality of signal paths.

15. The method as recited in claim 14, wherein for a given one of the plurality of test signal outputs, a corresponding one of the first plurality of signal paths has a length substantially the same as a corresponding one of the second plurality of signal paths.

16. The method as recited in claim 14 further comprising test signals output by the TAP arriving at the gold processor and the DUT in the same clock cycle.

17. The method as recited in claim 12 further comprising accessing the test output data from the gold processor and the test output data of the DUT independently from one another.

18. The method as recited in claim 16 further comprising outputting the test output data from the gold processor and the test output data of the DUT to a display unit.

19. The method as recited in claim 17 further comprising comparing the test output data from the gold processor and the test output data of the DUT.