Data Slicer Having An Error Correction Device
First Claim
1. A data slicer having an error correction device comprising:
- a first subtractor, for subtracting a first level signal from a first data signal to generate a second data signal;
a first serial to parallel converter, coupled to the first subtractor, for generating a first byte according to a sign bit of the second data signal;
a level compensator, coupled to the first subtractor, for adjusting an offset of the first level signal according to the second data signal to generate a second level signal;
a first comparator, coupled to the level compensator, for comparing the second level signal with the first data signal to generate a first comparing signal;
a second serial to parallel converter, coupled to the first comparator, for converting the first comparing signal to a second byte;
a co-channel detector, coupled to the level compensator, for determining co-channel interference according to a difference between a maximum and a minimum of the second level signal to generate a first indication signal;
an error bit predictor, coupled to the first subtractor, for indicating an error bit of the first byte to generate a second indication signal; and
an output device, for outputting the first byte or the second byte according to the first indication signal, a parity check of the first byte, and a parity check of the second byte, or outputting a corrected first byte according to the second indication signal.
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Accused Products
Abstract
A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.
10 Citations
12 Claims
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1. A data slicer having an error correction device comprising:
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a first subtractor, for subtracting a first level signal from a first data signal to generate a second data signal; a first serial to parallel converter, coupled to the first subtractor, for generating a first byte according to a sign bit of the second data signal; a level compensator, coupled to the first subtractor, for adjusting an offset of the first level signal according to the second data signal to generate a second level signal; a first comparator, coupled to the level compensator, for comparing the second level signal with the first data signal to generate a first comparing signal; a second serial to parallel converter, coupled to the first comparator, for converting the first comparing signal to a second byte; a co-channel detector, coupled to the level compensator, for determining co-channel interference according to a difference between a maximum and a minimum of the second level signal to generate a first indication signal; an error bit predictor, coupled to the first subtractor, for indicating an error bit of the first byte to generate a second indication signal; and an output device, for outputting the first byte or the second byte according to the first indication signal, a parity check of the first byte, and a parity check of the second byte, or outputting a corrected first byte according to the second indication signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A data slicer having an error correction device comprising:
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a first subtractor for subtracting a first level signal from a first data signal to generate a second data signal; a first serial to parallel converter coupled to the first subtractor for generating a first byte according to a sign bit of the second data signal; a first adder, for adding a predetermined offset to the first level signal; a first comparator, coupled to the first adder, for comparing an output signal of the first adder with the first data signal to generate a first comparing signal; a second serial to parallel converter, coupled to the first comparator, for converting the first comparing signal to a second byte; a second subtractor, for subtracting the predetermined offset from the first level signal; a second comparator, coupled to the second subtractor, for comparing an output signal of the second subtractor with the first data signal to generate a second comparing signal; a third serial to parallel converter, coupled to the second comparator, for converting the second comparing signal to a third byte; an error bit predictor, coupled to the first subtractor, for indicating an error bit of the first byte to generate a first indication signal; and an output device, for outputting the first byte, the second byte, or the third byte according to a parity check of the first byte, a parity check of the second byte, and a parity check of the third byte, or outputting a corrected first byte according to the first indication signal. - View Dependent Claims (10, 11, 12)
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Specification