Semiconductor integrated circuit device and fabrication method thereof

• US 20090044162A1
• Filed: 09/29/2008
• Published: 02/12/2009
• Est. Priority Date: 08/09/2002
• Status: Active Grant

• Current Assignee: Keiichi Yoshioka
• Original Assignee: Keiichi Yoshioka
• Inventors: Yoshioka, Keiichi
• Granted Patent: US 7,930,658 B2
• Time in Patent Office: Days
• US Class Current: 716/118
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.

Claims

1-13. -13. (canceled)

14. A method of fabricating a standard cell type semiconductor integrated circuit device having a plurality of semiconductor elements, the method comprising the steps of:

modularizing the plurality of semiconductor elements for each function thereof so as to form a plurality of function modules;

maintaining the plurality of function modules as standard cells in a library; and

arranging the standard cells in the standard cell type semiconductor integrated circuit device,

wherein at least one of the standard cells comprises a heat conduction part, said heat conduction part comprising the same conductive materials as a connection hole and a metal wiring layer constituting a multi-layer wiring structure, said heat conduction part extending toward an upper layer side along a path different from a wiring path comprising a connection hole and a metal wiring layer for signal transmission.

15. The method as claimed in claim 14, wherein the standard cell type semiconductor integrated circuit device comprises at least one field cell being arranged in an empty space between the function modules, said field cell comprising a heat conduction part comprising the same conductive materials as a connection hole and a metal wiring layer constituting a multi-layer wiring structure, said heat conduction part extending toward an upper layer side along a path different from a wiring path comprising a connection hole and a metal wiring layer for signal transmission.