METHOD OF FORMING AN MOS TRANSISTOR AND STRUCTURE THEREFOR

• US 20090045440A1
• Filed: 08/17/2007
• Published: 02/19/2009
• Est. Priority Date: 03/06/2006
• Status: Active Grant

• Current Assignee: Francine Y. Robb, Gordon M. Grivna
• Original Assignee: Francine Y. Robb, Gordon M. Grivna
• Inventors: Grivna, Gordon M., Robb, Francine Y.
• Granted Patent: US 8,350,318 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.

Claims

1. An MOS transistor comprising:

a substrate having a first conductivity type;

a body region of the transistor formed as a first doped region of a second conductivity type in the substrate and electrically coupled to a conductor;

an opening extending into the substrate and into the first doped region, the opening having a sidewall; and

a gate structure of the MOS transistor within the opening, the gate structure including a first insulator having a first thickness along a first portion of the sidewall and also including a second insulator having a second thickness along another portion of the sidewall wherein the second thickness is greater than the first thickness.

2. The MOS transistor of claim 1 further including a gate conductor within the opening and juxtaposed to the first insulator.

3. The MOS transistor of claim 1 further including a second doped region of the first conductivity type overlying the first doped region and wherein the first insulator is juxtaposed to a portion of the first doped region and the second insulator is juxtaposed a portion of the second doped region.

4. The MOS transistor of claim 3 further including a third doped region of the first conductivity type overlying a portion of the second doped region.

5. The MOS transistor of claim 4 wherein the third doped region is spaced a first distance away from the second insulator.

6. The MOS transistor of claim 4 wherein the third doped region has a peak doping concentration that is greater than a peak doping concentration of the second doped region.

7. The MOS transistor of claim 3 wherein the second doped region is coupled to a first conductor and the body region is electrically coupled to a second conductor that is not directly connected to the first conductor.

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