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Structure and Method of Sub-Gate NAND Memory with Bandgap Engineered SONOS Devices

  • US 20090045452A1
  • Filed: 07/17/2008
  • Published: 02/19/2009
  • Est. Priority Date: 05/23/2006
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a semiconductor body;

    a plurality of AND device structures, comprising;

    a first plurality of parallel structures over the semiconductor body, respective parallel structures in the first plurality of parallel structures including a sub-gate positioned to create an inversion layer in the semiconductor body under the respective parallel structure in the first plurality of parallel structures; and

    a second plurality of parallel structures over the semiconductor body, the second plurality of parallel structures having a substantially perpendicular orientation relative to the first plurality of parallel structures, respective parallel structures in the second plurality of parallel structures including;

    a tunneling dielectric layer on the semiconductor body;

    a charge trapping layer on the tunnel dielectric layer;

    a blocking dielectric layer on the charge trapping layer; and

    a control gate on the blocking dielectric layer.

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