Structure and Method of Sub-Gate NAND Memory with Bandgap Engineered SONOS Devices

• US 20090045452A1
• Filed: 07/17/2008
• Published: 02/19/2009
• Est. Priority Date: 05/23/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lien, Hao Ming, LUE, Hang-Ting
• Granted Patent: US 7,948,799 B2
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices with sub-gate lines and diffusion bit lines. In another example, a BE-SONOS sub-gate-AND architecture has multiple strings of SONONOS devices with sub-gate lines, relying on the sub-gate lines that create inversions to substitute for the diffusion bit lines.

Claims

1. An integrated circuit, comprising:

a semiconductor body;

a plurality of AND device structures, comprising;

a first plurality of parallel structures over the semiconductor body, respective parallel structures in the first plurality of parallel structures including a sub-gate positioned to create an inversion layer in the semiconductor body under the respective parallel structure in the first plurality of parallel structures; and

a second plurality of parallel structures over the semiconductor body, the second plurality of parallel structures having a substantially perpendicular orientation relative to the first plurality of parallel structures, respective parallel structures in the second plurality of parallel structures including;

a tunneling dielectric layer on the semiconductor body;

a charge trapping layer on the tunnel dielectric layer;

a blocking dielectric layer on the charge trapping layer; and

a control gate on the blocking dielectric layer.

2. The circuit of claim 1, wherein the respective parallel structures in the second plurality of parallel structures are positioned to create a read current in the semiconductor body under the respective parallel structure in the second plurality of parallel structures.

3. The circuit of claim 1, wherein:

the tunneling dielectric layer includes a first silicon oxide layer adjacent the semiconductor body and having a thickness of 30 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å

or less, and

the charge trapping layer comprises silicon nitride having a thickness of 50 Å

or more.

4. The circuit of claim 1, wherein:

the tunneling dielectric layer includes a first silicon oxide layer adjacent the semiconductor body and having a thickness of 15 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 35 Å

or less, and

the charge trapping layer comprises silicon nitride having a thickness of 50 Å

or more.

5. The circuit of claim 1, further comprising:

circuitry coupled to the plurality of AND device structures, the circuitry providing at least one bias arrangement to cause hole tunneling across the tunneling dielectric layer.

6. The circuit of claim 1, wherein the respective parallel structures in the second plurality of parallel structures are positioned to create a read current in the semiconductor body under the respective parallel structure in the second plurality of parallel structures, and

wherein the read current electrically connects to at least one inversion layer created by at least one of the first plurality of parallel structures, the read current having a magnitude varying with charge at the charge trapping layer.

7. The circuit of claim 1, wherein every other parallel structure of the first plurality of parallel structures is electrically interconnected.

8. The circuit of claim 1, wherein every fourth parallel structure of the first plurality of parallel structures is electrically interconnected.

9. The circuit of claim 1, wherein the plurality of AND device structures further comprises:

a plurality of parallel diffusions in the semiconductor body, the plurality of plurality of parallel diffusions being parallel to the first plurality of parallel structures.

10. The circuit of claim 1, wherein the plurality of AND device structures further comprises:

a plurality of parallel diffusions in the semiconductor body, the plurality of plurality of parallel diffusions being parallel to the first plurality of parallel structures,

wherein the respective parallel structures in the second plurality of parallel structures are positioned to create a read current in the semiconductor body under the respective parallel structure in the second plurality of parallel structures, and

wherein the read current is electrically connected to at least one parallel diffusion of the plurality of parallel diffusions.

11. The circuit of claim 1, wherein the respective parallel structures in the second plurality of parallel structures are positioned to create a read current in the semiconductor body under the respective parallel structure in the second plurality of parallel structures, and

wherein the read current is electrically connected to at least two inversion layers created on both sides of the respective parallel structure in the second plurality of parallel structures, the read current having a magnitude varying with charge at the charge trapping layer.

12. The circuit of claim 1, wherein the respective parallel structures in the second plurality of parallel structures are positioned to create a read current in the semiconductor body under the respective parallel structure in the second plurality of parallel structures, and

wherein the read current is electrically connected to at least two inversion layers created on both sides of the respective parallel structure in the second plurality of parallel structures, parallel diffusions in the semiconductor body being absent between said at least two inversion layers, the read current having a magnitude varying with charge at the charge trapping layer.

13. The circuit of claim 1, wherein the first plurality of parallel structures are positioned to perform source-side injection during programming.

14. An integrated circuit, comprising:

a semiconductor body;

a first device structure positioned to create a read current in the semiconductor body under the first device structure, including;

a tunneling dielectric layer on the semiconductor body;

a charge trapping layer on the tunnel dielectric layer;

a blocking dielectric layer on the charge trapping layer; and

a control gate on the blocking dielectric layer; and

a second device structure proximate to the first device structure and including a sub-gate positioned to create an inversion layer in the semiconductor body under the second device structure to control read access of the adjacent first device structure without controlling read access of nonadjacent device structures.