SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
First Claim
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1. A method for fabricating a semiconductor device, the method comprising:
- etching a substrate to form a recess pattern;
forming a gate dielectric layer over the recess pattern;
forming a gate electrode over the gate dielectric layer inside the recess pattern, wherein the gate electrode does not extend above a surface of the substrate;
forming a gate hard mask pattern over the gate electrode and upper corners of the recess pattern; and
forming a plug over the substrate between the gate hard mask pattern and an adjacent gate hard mask pattern.
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Abstract
A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate electrode is not exposed above the substrate, it is possible to prevent SAC failure and decrease an aspect ratio of a gate pattern to increase an open margin of a contact hole. Thus, a semiconductor device having a recess channel gate structure which exhibits a superior refresh property is fabricated.
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Citations
25 Claims
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1. A method for fabricating a semiconductor device, the method comprising:
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etching a substrate to form a recess pattern; forming a gate dielectric layer over the recess pattern; forming a gate electrode over the gate dielectric layer inside the recess pattern, wherein the gate electrode does not extend above a surface of the substrate; forming a gate hard mask pattern over the gate electrode and upper corners of the recess pattern; and forming a plug over the substrate between the gate hard mask pattern and an adjacent gate hard mask pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A semiconductor device comprising:
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a recess pattern formed in a substrate; a gate dielectric layer formed over the recess pattern; a gate electrode formed over the gate dielectric layer inside the recess pattern, wherein the gate electrode does not extend above a surface of the substrate; a gate hard mask pattern formed over the gate electrode and upper corners of the recess pattern; and a plug formed over the substrate between the gate hard mask pattern and an adjacent gate hard mask pattern. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification