MICROELECTRONIC DIE PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAME-BASED INTERPOSER FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS

• US 20090045489A1
• Filed: 10/24/2007
• Published: 02/19/2009
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Koon, Eng Meow, Yean, Tay Wuu
• Granted Patent: US 7,947,529 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49527 the additional leads being a multilayer
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]

Abstract

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Claims

1. A method for forming a microelectronic device, the method comprising:

stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing;

aligning first metal leads at a first lateral surface of the first casing with second metal leads at a second lateral surface of the second casing; and

forming external inter-package connectors that couple individual first leads to individual second leads along, at least in part, the first and second lateral surfaces.

2. The method of claim 1, wherein forming the external inter-package connectors comprises applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package, wherein the connectors are formed by a process that includes the metal solder wetting to the individual first leads and the individual second leads.

3. The method of claim 2, wherein applying the metal solder further comprises applying a liquid-phase metal solder to the portion of the first lateral surface and the portion of the second lateral surface.

4. The method of claim 2, wherein applying the metal solder further comprises:

applying a solder paste having metal powder particles to the portion of the first lateral surface and the portion of the second lateral surface; and

heating the solder paste.

5. The method of claim 2, wherein applying the metal solder across the gap includes spacing the first die package apart from the second die package so that surface tension associated with the metal solder creates metal solder bridges between the individual first leads and the individual second leads.

6. The method of claim 2, further comprising using the metal solder to selectively electrically couple a portion of the first leads with a portion of the second leads.

7. The method of claim 1, wherein the connectors are further coupled to the individual first leads at a bottom-side surface portion of the first casing and to the individual second leads at a top-side surface portion of the second casing.

8. The method of claim 1, further comprising coupling package bond pads of the second die package to metal bump pads associated with an interposer substrate.

9. A method for forming a microelectronic device, the method comprising:

encapsulating at least a portion of a microelectronic die and a metal frame in a dielectric material so that the dielectric material fills gaps between lateral edges of the die and the frame and gaps between metal lead portions of the frame;

forming lateral surfaces of a package spaced apart from the lateral edges of the die and lateral conductive contact surfaces of individual lead portions flush with the lateral surfaces of the package; and

forming top-side contact surfaces and/or bottom-side contact surfaces of the individual lead portions, wherein the individual lead portions are configured so that inter-package metal solder connectors wet at least along the lateral contact surfaces of the individual lead portions.

10. The method of claim 9, wherein forming the top-side contact surfaces and/or the bottom-side contact surfaces of the individual lead portions comprises planarizing a portion of the dielectric material.

11. The method of claim 9, wherein forming the lateral surfaces of the packages and forming the lateral contact surfaces of the individual lead portions includes cutting through the metal frame and the dielectric material.

12. The method of claim 9, wherein the frame is coupled to a support substrate for molding a bottom side of the dielectric material.

13. The method of claim 12, further comprising:

removing the support substrate to expose an active side of the die; and

forming metal traces that route active features of the die to the individual lead portions.

14. The method of claim 13, further comprising forming package bond pads that are coupled to the individual lead portions and individual metal traces.

15. The method of claim 9, further comprising thinning a portion of the frame so that the dielectric material projects above a top-side surface of the lead portions.

16. A stacked system of microelectronic die packages, comprising:

a first microelectronic die package including a first die and a first dielectric casing at least partially covering the first die, lateral surfaces along the first casing, and first metal contacts having first lateral contact surfaces along the lateral surfaces of the first casing;

a second microelectronic die package including a second die and a second dielectric casing at least partially covering the second die, lateral surfaces along the second casing, and second metal contacts having second lateral contact surfaces along the lateral surfaces of the second casing, wherein the second package is stacked on top of the first package and the first metal contacts are at least generally aligned with corresponding second metal contacts; and

metal solder connectors coupled to individual first metal contacts and individual second metal contacts, wherein at least a portion of the connectors contact the first and second lateral contact surfaces.

17. The stacked system of claim 16, wherein at least a portion of the connectors projects laterally outward from the lateral contact surfaces of the first and second casings.

18. The stacked system of claim 16, wherein the connectors further project laterally inward between the first package and the second package.

19. The stacked system of claim 16, wherein the first metal contacts further include first top-side contact surfaces and first bottom-side contact surfaces, the second metal contacts further include second top-side contact surfaces and second bottom-side contact surfaces, and wherein individual connectors are further coupled to one of the first top-side surfaces and a corresponding one of the second bottom-side surfaces.

20. The stacked system of claim 16, wherein the first die has a first lateral dimension and the second die has a second lateral dimension different than the first lateral dimension, and wherein the first and second casings have equal lateral dimensions.

21. A computing system, comprising at least one of a processor, a memory, and an input/device, wherein the computing system includes the stacked system according to claim 16.

22. A stacked system of microelectronic die packages, comprising:

a first die package having a first lateral edge and first metal leads having first contact surfaces flush with the first lateral edge;

a second die package having a second lateral edge and second metal leads having second contact surfaces flush with the second lateral edge and generally aligned with the first lateral contact surfaces; and

external electrically conductive inter-package connectors, wherein individual inter-package connectors are connected to one of the first contact surfaces and a corresponding second contact surface, and wherein the connectors comprise individual metal solder lines that bridge a gap between the first and second packages.

23. The stacked system of claim 22, wherein the gap spans a lateral distance of up to 60 microns.

24. The stacked system of claim 22, wherein the first package comprises a first dielectric material that is configured to separate the individual first leads apart from each other, and wherein the second package comprises a second dielectric material that is configured to separate the individual second leads apart from each other.

25. The stacked system of claim 24, wherein the first dielectric material has a top-side surface that is configured so that the individual first leads are coupled with a top-side of the first package.

26. The stacked system of claim 24, wherein the second dielectric material has a bottom-side surface that is configured so that the individual second leads are coupled with a bottom-side of the second package.

27. A microelectronic device, comprising:

a molded dielectric material having lateral-side, bottom-side, and top-side surfaces;

a microelectronic die at least partially encapsulated within the dielectric material and spaced laterally apart from the lateral surface of the dielectric material; and

individual metal leads electrically coupled with the die and having a wetting surface configured for attaching external inter-package solder lines, wherein the wetting surface includes an exposed metal portion that is flush with the lateral surface of the dielectric material and at least one of the top-side and bottom-side surfaces of the dielectric material.

28. The microelectronic device of claim 27, further comprising a dielectric spacer layer coupled to a bottom side of the die for electrically isolating active features of the die.

29. The microelectronic device of claim 28, further comprising metal traces for coupling the leads to the active features.

30. The microelectronic device of claim 29, wherein the metal traces are configured to selectively electrically couple integrated circuitry of the die with the leads.

31. The microelectronic device of claim 27, wherein the top-side surface of the dielectric material is substantially planar for package-to-package stacking.

32. The microelectronic device of claim 27, wherein the leads have a lateral thickness that is at least 650 microns.

33. The microelectronic device of claim 27, wherein the dielectric material has a lateral thickness that is at least 650 microns.