ADVANCED REPEATER WITH DUTY CYCLE ADJUSTMENT
First Claim
Patent Images
1. A circuit for assisting transitions of a signal on a wire, said circuit comprising:
- an output stage for driving an output signal line responsive to an input signal; and
a plurality of active devices for selectably adjusting a duty cycle of said signal.
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Abstract
An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.
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Citations
20 Claims
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1. A circuit for assisting transitions of a signal on a wire, said circuit comprising:
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an output stage for driving an output signal line responsive to an input signal; and a plurality of active devices for selectably adjusting a duty cycle of said signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of assisting transitions of an input signal, said method comprising:
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receiving a transition of said input signal at a circuit input; receiving a plurality of control signals to selectively adjust the duty cycle of an output signal generally corresponding to said input signal; selectively adjusting said duty cycle; driving an output level corresponding to said transition; and ceasing said driving prior to an arrival at said circuit input of a subsequent transition of said signal. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A circuit for assisting signal transitions on a wire, said circuit comprising:
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a first transistor for driving a rising edge transition on an output signal line; a second transistor for driving a falling edge transition on said output signal line; an OR gate having first and second inputs for controlling said first transistor; said OR gate further comprising a plurality of pull up transistors for selectably adjusting timing of said rising edge transition; an AND gate having first and second inputs for controlling said second transistor; and said AND gate further comprising a plurality of pull down transistors for selectably adjusting timing of said falling edge transition. - View Dependent Claims (18, 19, 20)
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Specification