PHASE-FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE

• US 20090045848A1
• Filed: 08/15/2007
• Published: 02/19/2009
• Est. Priority Date: 08/15/2007
• Status: Abandoned Application

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Socci, Gerard G., Bahai, Ahmad, Kiaei, Ali, Djabbari, Ali
• Application Number:
  US11/839,018
• Publication Number:
  US 20090045848A1
• Time in Patent Office: Days
• US Class Current: 327/10
• CPC Class Codes: H03D 13/00 Circuits for comparing the phase or frequency of two mutually-independent oscillations measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005

Abstract

A phase-frequency detection system and method for enhancing performance of the frequency detector in a phase-frequency detection system. Filtering of the frequency detector inputs makes operation of the frequency detector more robust in the presence of intersymbol interference within the incoming data signal and other non-ideal characteristics such as noise and crosstalk.

Claims

1. An apparatus including a phase-frequency detector for use in detecting a clock signal associated with an incoming data signal, comprising:

a data electrode to convey a binary data signal having a clock signal associated therewith;

a plurality of clock electrodes to convey a plurality of clock signals having a like plurality of mutually dissimilar clock signal phases;

phase detection circuitry coupled to said data electrode and said plurality of clock electrodes, and responsive to said binary data signal and said plurality of clock signals by providing first and second beat signals corresponding to first and second samples of one or more of said binary data signal and plurality of clock signals;

filter circuitry coupled to said phase detection circuitry and responsive to said first and second beat signals by providing corresponding first and second filtered signals; and

frequency detection circuitry coupled to said filter circuitry and responsive to said first and second filtered signals by providing a detection signal having a value indicative of a frequency difference between said binary data signal and at least one of said plurality of clock signals.

2. The apparatus of claim 1, wherein said plurality of clock electrodes comprises first and second clock electrodes, and said plurality of mutually dissimilar clock signal phases comprises first and second mutually quadrature signal phases.

3. The apparatus of claim 1, wherein:

said plurality of clock electrodes comprises first, second, third and fourth clock electrodes; and

said plurality of mutually dissimilar clock signal phases comprises first and second mutually quadrature signal phases, and third and fourth mutually quadrature signal phases.

4. The apparatus of claim 1, wherein said phase detection circuitry is responsive to said binary data signal and said plurality of clock signals by providing first and second beat signals corresponding to first and second samples of said binary data signal.

5. The apparatus of claim 1, wherein said phase detection circuitry comprises a plurality of half-rate phase detector circuits.

6. The apparatus of claim 1, wherein said phase detection circuitry comprises:

a first phase detector circuit responsive to said binary data signal and a first portion of said plurality of clock signals by providing said first beat signal; and

a second phase detector circuit responsive to said binary data signal and a second portion of said plurality of clock signals by providing said second beat signal.

7. The apparatus of claim 1, wherein said filter circuitry comprises:

a first low pass filter circuit responsive to said first beat signal by providing a first low pass filtered signal; and

a second low pass filter circuit responsive to said second beat signal by providing a second low pass filtered signal.

8. The apparatus of claim 1, wherein said filter circuitry performs first and second nonlinear majority vote operations.

9. The apparatus of claim 1, wherein said frequency detection circuitry comprises a half-rate frequency detector circuit.

10. The apparatus of claim 1, wherein said frequency detection circuitry is responsive to said first and second filtered signals by providing a ternary signal as said detection signal.

11. An apparatus including a phase-frequency detector for use in detecting a clock signal associated with an incoming data signal, comprising:

phase detector means for detecting a binary data signal having a clock signal associated therewith and a plurality of clock signals having a like plurality of mutually dissimilar clock signal phases to provide first and second beat signals corresponding to first and second samples of one or more of said binary data signal and plurality of clock signals;

filter means for filtering said first and second beat signals to provide corresponding first and second filtered signals; and

frequency detector means for detecting said first and second filtered signals to provide a detection signal having a value indicative of a frequency difference between said binary data signal and at least one of said plurality of clock signals.

12. A method of phase-frequency detection for use in detecting a clock signal associated with an incoming data signal, comprising:

detecting a binary data signal having a clock signal associated therewith and a plurality of clock signals having a like plurality of mutually dissimilar clock signal phases to provide first and second beat signals corresponding to first and second samples of one or more of said binary data signal and plurality of clock signals;

filtering said first and second beat signals to provide corresponding first and second filtered signals; and

detecting said first and second filtered signals to provide a detection signal having a value indicative of a frequency difference between said binary data signal and at least one of said plurality of clock signals.

13. The method of claim 12, wherein said detecting a binary data signal and a plurality of clock signals to provide first and second beat signals comprises detecting said binary data signal and first and second clock signals, wherein said first and second clock signals have first and second mutually quadrature signal phases.

14. The method of claim 12, wherein said detecting a binary data signal and a plurality of clock signals to provide first and second beat signals comprises detecting said binary data signal and first, second, third and fourth clock signals, wherein said first, second, third and fourth clock signals have first and second mutually quadrature signal phases, and third and fourth mutually quadrature signal phases.

15. The method of claim 12, wherein said detecting a binary data signal and a plurality of clock signals to provide first and second beat signals comprises detecting said binary data signal and plurality of clock signals to provide first and second beat signals corresponding to first and second samples of said binary data signal.

16. The method of claim 12, wherein said detecting a binary data signal and a plurality of clock signals to provide first and second beat signals comprises detecting said binary data signal and plurality of clock signals via half-rate phase detection.

17. The method of claim 12, wherein said detecting a binary data signal and a plurality of clock signals to provide first and second beat signals comprises:

detecting said binary data signal and a first portion of said plurality of clock signals to provide said first beat signal; and

detecting said binary data signal and a second portion of said plurality of clock signals to provide said second beat signal.

18. The method of claim 12, wherein said filtering said first and second beat signals to provide corresponding first and second filtered signals comprises:

filtering said first beat signal to provide a first low pass filtered signal; and

filtering said second beat signal to provide a second low pass filtered signal.

19. The method of claim 12, wherein said detecting said first and second filtered signals to provide a detection signal comprises detecting said first and second filtered signals via half-rate frequency detection.

20. The method of claim 12, wherein said detecting said first and second filtered signals to provide a detection signal comprises detecting said first and second filtered signals to provide a ternary signal as said detection signal.