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CLOCK SIGNAL SYNCHRONIZING DEVICE WITH INHERENT DUTY-CYCLE CORRECTION CAPABILITY

  • US 20090045856A1
  • Filed: 08/14/2007
  • Published: 02/19/2009
  • Est. Priority Date: 08/14/2007
  • Status: Active Grant
First Claim
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1. A clock signal synchronizing device comprising:

  • a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal;

    a negator for inverting the delayed clock signal to output an inverted delayed clock signal;

    a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal;

    a phase interpolator; and

    a phase interpolator control circuit;

    wherein the phase interpolator adds the incoming clock signal multiplied with a factor of substantially (1−

    p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1; and

    wherein the phase interpolator control circuit sets the value of p to substantially 0 when the incoming clock signal and the inverted delayed clock signal are not in phase, and sets the value of p to a value greater than 0 and smaller than or equal to 1 when the incoming clock signal and the inverted delayed clock signal are substantially in phase.

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