System and method for multi-protocol radio-frequency identification

• US 20090045921A1
• Filed: 08/16/2007
• Published: 02/19/2009
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Farpointe Data Incorporated (dormakaba Holding AG)
• Original Assignee: Farpointe Data Incorporated (dormakaba Holding AG)
• Inventors: Bierach, Kirk B., Nelson, Christopher J.
• Granted Patent: US 8,411,764 B2
• Time in Patent Office: Days
• US Class Current: 340/10.200
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10297 arrangements for handling protocols designed for non-contact record carriers such as RFIDs NFCs, e.g. ISO/IEC 14443 and 18092 cryptographic protocols H04L9/00; network security protocols H04L63/00; real-time communication protocols in data switching networks H04L65/00; network protocols for data switching network services H04L67/00

Abstract

A system and method for communicating with contactless IC cards of multiple protocols includes transmitting an IC card polling signal and receiving a data transmission from an IC card. A processor is configured to determine whether or not a data transmission is received in response to the polling signal. The processor is configured to decode the data transmission in real-time if it is received in response to the polling signal. The processor is otherwise configured to first store the received data transmission in a memory and then decode the stored data transmission.

Claims

1. A method for communicating with a contactless IC card, the method comprising:

transmitting an IC card polling signal;

receiving a data transmission from an IC card;

determining whether or not the data transmission is being received in response to the polling signal;

decoding in real-time the data transmission being received when the data transmission is being received in response to the polling signal; and

storing the received data transmission in a memory and decoding the stored data transmission when the data transmission is not being received in response to the polling signal.

2. The method of claim 1, wherein determining whether or not the data transmission is being received in response to the polling signal comprises determining whether the data transmission being received before or after expiration of a first time period following transmission of the polling signal.

3. The method of claim 2, wherein decoding the data transmission stored in the memory comprises determining a format of the stored data transmission, which includes:

determining whether the data transmission includes one or more start bits;

determining whether the data transmission includes one or more parity bits; and

determining whether the data transmission includes one or more cyclic redundancy check (CRC) bits.

4. The method of claim 3, wherein determining whether the data transmission includes one or more start bits includes:

determining the total number of bits in the data transmission; and

determining whether the total number of bits in the data transmission is divisible without remainder by at least one of a first integer and a second integer.

5. The method of claim 4, further comprising:

removing the one or more start bits from the data transmission.

6. The method of claim 5, wherein determining whether the data transmission includes one or more parity bits includes:

determining whether the total number of bits in the data transmission, less the one or more start bits, is divisible without a remainder by at least one of the first integer and the second integer.

7. The method of claim 6, further comprising:

determining, based on the values of one or more parity bits, a parity of the data transmission, the parity including one of even parity and odd parity;

detecting an error in the data transmission, based on the parity of the data transmission and the values of the one or more parity bits in the data transmission; and

removing the one or more parity bits from the data transmission when no error in the data transmission is detected.

8. The method of claim 7, wherein determining whether the data transmission includes one or more CRC bits includes:

performing a cyclic redundancy check of the data transmission; and

removing the CRC bits from the data transmission when the cyclic redundancy check is completed.

9. The method of claim 8, wherein the first integer is eight and the second integer is nine.

10. The method of claim 9, further comprising:

retransmitting the polling signal after expiration of a second time period, the second time period being longer than the first time period.

11. A system for communicating with a contactless IC card, comprising:

a transmitter configured to transmit an IC card polling signal;

a receiver configured to detect a data transmission from an IC card;

a memory configured to store the detected data transmission; and

a processor configured to

determine whether or not the data transmission is being received in response to the polling signal;

decode in real-time the data transmission being received when the data transmission is being received in response to the polling signal; and

store the received data transmission in a memory and decode the stored data transmission when the data transmission is not being received in response to the polling signal.

12. The system of claim 11, wherein to determine whether or not the data transmission is being received in response to the polling signal, the processor is configured to determine whether the data transmission is being received before or after expiration of a first time period following transmission of the polling signal.

13. The system of claim 12, wherein to decode the stored data transmission, the processor is further configured to determine a format of the data transmission, wherein in order to determine the format of the data transmission, the processor is further configured to determine whether the data transmission includes one or more start bits;

to determine whether the data transmission includes one or more parity bits; and

to determine whether the data transmission includes one or more cyclic redundancy check (CRC) bits.

14. The system of claim 13, wherein to determine whether the data transmission includes one or more start bits, the processor is further configured:

to determine the total number of bits in the data transmission; and

to determine whether the total number of bits in the data transmission is divisible without remainder by at least one of a first integer and a second integer.

15. The system of claim 14, wherein the processor is further configured to remove the one or more start bits from the data transmission.

16. The system of claim 15, wherein to determine whether the data transmission includes one or more parity bits, the processor is further configured to determine whether the total number of bits in the data transmission, less the one or more start bits, is divisible without a remainder by at least one of the first integer and the second integer.

17. The system of claim 16, wherein the process is further configured to determine, based on the values of one or more parity bits, a parity of the data transmission, the parity including one of even parity and odd parity.

18. The system of claim 17, wherein the processor is further configured:

to detect an error in the data transmission, based on the parity of the data transmission and the values of the one or more parity bits in the data transmission; and

to remove the one or more parity bits from the data transmission when no error in the data transmission is detected.

19. The system of claim 17, wherein to determine whether the data transmission includes one or more CRC bits, the processor is further configured:

to perform a cyclic redundancy check of the data transmission; and

to remove the one or more CRC bits from the data transmission when the cyclic redundancy check is completed.

20. The system of claim 19, wherein the first integer is eight and the second integer is nine.

21. The system of claim 11, wherein the memory includes one of a memory buffer and a random access memory.

22. The system of claim 11, wherein the processor includes at least one of a general purpose microprocessor, a microcontroller, a field programmable gate array and an application specific integrated circuit (ASIC).

23. The system of claim 11, wherein the contactless IC card includes an RFID card.

24. A programmable integrated circuit (IC) device for facilitating communication with a contactless IC card, the IC device comprising program logic for:

generating a bit sequence for transmission as a polling signal to an IC card;

receiving a bit sequence generated from a data transmission from an IC card;

determining whether or not the data transmission is being received in response to the polling signal; and

decoding in real-time the bit sequence being received when the data transmission is being received in response to the polling signal; and

storing the received bit sequence in a memory and decoding the stored bit sequence when the data transmission is not being received in response to the polling signal.

25. The programmable IC device of claim 24, wherein to determine whether or not the data transmission is being received in response to the polling signal, the programmable IC device includes program logic for determining whether the data transmission being received before or after expiration of a first time period following transmission of the polling signal.

26. The programmable IC device of claim 25, wherein to decode the bit sequence stored in the memory, the programmable IC device includes program logic for determining format of the bit sequence, including program logic for:

determining whether the bit sequence includes one or more start bits;

determining whether the bit sequence includes one or more parity bits; and

determining whether the bit sequence includes one or more CRC bits.

27. The programmable IC device of claim 26, wherein the programmable IC device includes at least one of a general purpose microprocessor, a microcontroller, a field programmable gate array, and an application specific integrated circuit (ASIC).

28. The programmable IC device of claim 27, wherein the contactless IC card includes an RFID card.

29. A computer-readable medium comprising computer-executable instructions for configuring operation of a contactless IC card interrogator, comprising instructions for selecting an operating mode of the IC card interrogator, wherein the operating mode being selected from a group of operating modes including:

a first operating mode, wherein the IC card interrogator initiates communication with proximate IC cards by periodically transmitting an IC card polling signal;

a second operating mode, wherein an IC card interrogator listens for communications initiated by proximate IC cards; and

a third operating mode, wherein the IC card interrogator periodically alternates between the first operating mode and the second operating mode.

30. The computer-readable medium of claim 29, further comprising instructions for configuring duration of the first operating mode and duration of the second operating mode when the third operating mode is selected.

31. The computer-readable medium of claim 30, further comprising instructions for

retrieving from the interrogator information communicated by an IC card;

and

displaying the retrieved information in human-readable form.

32. The computer-readable medium of claim 30, further comprising instructions for

retrieving from the interrogator information communicated by an IC card;

decoding the retrieved information; and

displaying the decoded information in human-readable form.