CIRCUIT AND METHOD FOR CONTROLLING REFRESH PERIODS IN SEMICONDUCTOR MEMORY DEVICES

• US 20090046531A1
• Filed: 04/29/2008
• Published: 02/19/2009
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jong-Hyun, Noh, Kwang-Sook, Seo, Young-Hun
• Granted Patent: US 7,843,752 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/402 with charge regeneration individual to each memory cell, i.e. internal refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning

Abstract

An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Claims

1. An integrated circuit memory device, comprising:

a refresh control circuit configured to generate an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device, in response to detecting a change in temperature of the memory device.

2. The memory device of claim 1, wherein said refresh control circuit is further configured to generate an internal memory refresh command signal having a period that is increased relative to the period of the external memory refresh command signal, in response to detecting a reduction in temperature of the memory device.

3. The memory device of claim 1, wherein said refresh control circuit comprises a temperature information storage device configured to generate a first signal having a value that is changed in response to a first change in temperature of the memory device.

4. The memory device of claim 3, wherein said refresh control circuit further comprises:

a counter configured to generate a second signal in response to the external memory refresh command signal; and

a comparator responsive to the first and second signals, said comparator configured to generate a comparison signal having a value that identifies when the first and second signals are equivalent.

5. The memory device of claim 4, wherein said refresh control circuit further comprises a refresh command signal generator configured to generate the internal memory refresh command signal in response to the comparison signal.

6. The memory device of claim 5, wherein the internal memory refresh command signal is a pulse train having a non-uniform duty cycle;

and wherein leading edges of the pulses in the pulse train are synchronized with respective changes in the comparison signal that reflect an equivalency between the first and second signals.

7. The memory device of claim 4, wherein said counter is configured to generate the second signal as a repeating sequence of count values that change in-sync with leading edges of the external memory refresh command signal.

8. The memory device of claim 3, wherein said refresh control circuit further comprises:

a refresh command signal generator configured to generate at least a first refresh command signal having a period N times greater than a period of the external memory refresh command signal, where N is an integer greater than one.

9. The memory device of claim 8, wherein said refresh control circuit further comprises a multiplexer having a first data input configured to receive the external memory refresh command signal and a second data input configured to receive the first refresh command signal.

10. The memory device of claim 9, wherein said refresh control circuit further comprises a temperature sensor configured to measure a temperature of the memory device;

and wherein a control input of the multiplexer is configured to receive an output of the temperature sensor.

11. A circuit for controlling a refresh period in a semiconductor memory device to decide the refresh period depending upon a temperature, the circuit comprising:

a temperature sensing unit for outputting a measured internal temperature of the semiconductor memory device;

a counting unit for counting the input number of external refresh commands repeatedly input every specific period, and outputting the counted number; and

a control unit for generating an internal refresh command in response to the external refresh command, by deciding a generation of the internal refresh command depending upon the measured temperature input from the temperature sensing unit and the counted number input from the counting unit.

16. A circuit for controlling a refresh period in a semiconductor memory device to decide the refresh period depending upon temperature, the circuit comprising:

a refresh command generating unit for receiving an external refresh command having a constant period, and generating a plurality of refresh commands having different periods; and

an internal refresh command selection unit for receiving a measured internal temperature of the semiconductor memory device, selecting one of the plurality of refresh commands, and outputting the command as an internal refresh command.

12. The circuit of claim 13, wherein the control unit is controlled to disregard an external refresh command that is input within a period of from a generation of one internal refresh command to a generation of subsequent internal refresh command.

13. The circuit of claim 16, wherein the control unit comprises:

an information storage for storing the disregarded number of external refresh commands based on a temperature interval, and outputting the disregarded number corresponding to the measured temperature;

an information comparator for comparing the counted number of external refresh commands input from the counting unit, with the disregarded number output from the information storage, and outputting a clarification signal when the counted number is equal to or more than the disregarded number; and

a signal generator for generating an internal refresh command in response to the clarification signal.

15. The circuit of claim 16, wherein when the disregarded number and the counted number are not equal to each other, the information comparator disregards the counted number until the disregarded number and the counted number become equal, and controls a generation of the clarification signal.

20. A method of controlling a refresh period in a semiconductor memory device to decide the refresh period depending upon temperature, the method comprising:

a first step of outputting a measured internal temperature of the semiconductor memory device, and outputting a counted number obtained by counting the input number of external refresh commands received from the outside; and

a second step of comparing whether a disregarded number of predetermined external refresh commands based on a specific temperature interval is equal to the counted number of the external refresh commands when the measured temperature is included into the specific temperature interval among predetermined temperature intervals, and deciding a generation of internal refresh command.

22. The method of claim 26, wherein the disregarded number of external refresh commands based on the temperature interval increases as the measured temperature becomes lower.

18. The circuit of claim 22, wherein the period converter is a D flip-flop.

23. A method of controlling a refresh period in a semiconductor memory device to divide an internal temperature into temperature intervals with a constant interval and to have different refresh periods based on each temperature interval, the method comprising:

a first step of receiving an external refresh command with a constant period from the outside; and

a second step of generating an internal refresh command having a period different from an input period of the external refresh command according to an internal temperature change of the semiconductor memory device.

24. The method of claim 28, wherein the second step comprises more lengthening a period of the internal refresh command regardless of a period of the external refresh command, as an internal temperature of the semiconductor memory device becomes lower.

25. The method of claim 29, wherein the second step comprises:

measuring an internal temperature of the semiconductor memory device;

clarifying a predetermined refresh period at a temperature interval including the measured internal temperature; and

generating an internal refresh command with the same period as the refresh period.

14. The circuit of claim 17, wherein the information storage classifies an internal temperature into temperature intervals according to an internal temperature change of the semiconductor memory device, and stores the disregarded number of the external refresh commands based on each temperature interval, and receives the measured temperature from the temperature sensing unit to output the disregarded number of external refresh commands corresponding to the measured temperature to the information comparator.

17. The circuit of claim 21, wherein the refresh command generating unit comprises at least one period converter for converting a period of input signal.

19. The circuit of claim 21, wherein the internal refresh command selection unit comprises at least one multiplexer for selecting one of a plurality of refresh commands in response to the measured temperature;

and

at least one temperature sensor for measuring internal temperature of the semiconductor memory device, and transmitting the temperature to the multiplexer.

21. The method of claim 25, wherein the second step comprises generating an internal refresh command in response to an external refresh command when the disregarded number and the counted number are equal, and controlling a generation of the internal refresh command when the disregarded number and the counted number are unequal.