Multichip system and method of transferring data therein

• US 20090046533A1
• Filed: 07/26/2005
• Published: 02/19/2009
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jo, Seong-Kue
• Granted Patent: US 7,710,758 B2
• Time in Patent Office: Days
• US Class Current: 365/230.30
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data to the second memory chip in response to local transfer information provided from the host system. The first memory chip controls the host system not to access the first and second memory chips while conducting a local transfer operation. According to the invention, since the data is able to be directly transferred between the memory chips without the host system, it enhances the efficiency of the multichip system and improves a data transfer speed.

Claims

1. A multichip system comprising:

first and second memory chips; and

a memory controller regulating operations of the first and second memory chips, wherein the first memory chip controls the second memory chip to make data transferred to the second memory chip in direct in response to local transfer information input from the memory controller.

2. The multichip system as set forth in claim 1, wherein the first memory chip provides a command to the second memory chip in direct.

3. The multichip system as set forth in claim 1, which further comprises a memory bus connecting the first and second memory chips in direct,

wherein data is transferred between the first and second memory chips by way of the memory bus.

4. The multichip system as set forth in claim 1, wherein the local transfer information includes a local transfer command, source and target addresses, and a data size to be transferred.

5. The multichip system as set forth in claim 1, wherein the first memory chip comprises:

a memory core storing data;

an interface unit cooperative to the second memory chip;

a control logic unit regulating an operation of the memory core in response to a command input from the interface unit; and

a local transfer controller regulating the interface unit to make data transferred to the second memory chip in response to the local transfer information and a local transfer beginning signal input from the control logic unit.

6. The multichip system as set forth in claim 5, wherein the local transfer beginning signal is generated when data stored in the memory core are all transferred to the control logic unit in a local transfer mode.

7. The multichip system as set forth in claim 5, wherein the first and second memory chips are same in kind.

8. A multichip system comprising:

first and second memory chips; and

first and second memory controllers regulating operations of the first and second memory chips, respectively,

wherein the first memory chip controls the second memory chip to make data transferred to the second memory chip in direct in response to local transfer information input from the second memory controller in a local transfer mode.

9. The multichip system as set forth in claim 8, wherein the first memory chip provides a command to the second memory chip in direct.

10. The multichip system as set forth in claim 8, which further comprises a memory bus connecting the first and second memory chips in direct,

wherein data is transferred between the first and second memory chips by way of the memory bus.

11. The multichip system as set forth in claim 8, wherein the local transfer information includes a local transfer command, source and target addresses, and a data size to be transferred.

12. The multichip system as set forth in claim 8, wherein the first memory chip comprises:

a memory core storing data;

a first interface unit cooperative to the first memory controller;

a second interface unit cooperative to the second memory controller and the second memory chip;

a control logic unit regulating an operation of the memory core in response to commands input from the first and second interface units; and

a local transfer controller regulating the interface unit to make data transf erred to the second memory chip in response to the local transfer information and a local transfer beginning signal input from the control logic unit.

13. The multichip system as set forth in claim 12, wherein the local transfer beginning signal is generated when data stored in the memory core are all transferred to the control logic unit in a local transfer mode.

14. The multichip system as set forth in claim 12, wherein the first and second memory chips are different from each other in kind.

15. A multichip system comprising:

first and second memory chips;

a host system controlling operations of the first and second memory chips; and

a memory bus connecting the first and second memory chips with each other in direct,

wherein the first memory chip provides a DMA request signal to the host system to disable the host system to access the first and second memory chips during a local transfer mode in response to local transfer information input from the host system, and provides a command to the second memory chip to enable data transferred in direct to the second memory chip by way of the memory bus in response to a DMA approval signal input from the host system.

16. The multichip system as set forth in claim 15, wherein the host system comprises:

a memory controller regulating operations of the first and second memory chips and providing the local transfer information; and

a DMA controller requesting a central processing unit to suspend a use of a system bus in response to the DMA request signal and generating the DMA approval signal from a grant by the central processing unit.

17. The multichip system as set forth in claim 16, wherein the memory controller is disabled to control operations of the first and second memory chips when the DMA approval signal is generated.

18. The multichip system as set forth in claim 16, wherein the memory controller comprises a tri-state buffer that is connected to a pad and conditioned in a floating state in response to the DMA approval signal.

19. The multichip system as set forth in claim 16, wherein the first memory chip comprises:

a memory core storing data;

an interface unit cooperative to the second memory chip;

a control logic unit regulating an operation of the memory core in response to a command input from the interface unit; and

a local transfer controller generating the DMA request signal in response to the local transfer information and a local transfer beginning signal input from the control logic unit, and regulating the interface unit to make data transferred to the second memory chip in response to the DMA approval signal.

20. The multichip system as set forth in claim 19, wherein the local transfer beginning signal is generated when data stored in the memory core are all transferred to the control logic unit in the local transfer mode.

21. The multichip system as set forth in claim 16, wherein the first and second memory chips are same in kind.

22. A multichip system comprising:

first and second memory chips;

a memory bus connecting the first and second memory chips with each other in direct;

first and second memory controllers regulating operations of the first and second memory chips, respectively;

a system bus connecting the first and second memory controllers with each other; and

a DMA controller requesting a central processing unit to suspend a use of the system bus in response to a DMA request signal from the first memory chip, and generating the DMA approval signal from a grant by the central processing unit, wherein the first memory chip provides the DMA request signal in response to local transfer information input from the second memory controller, and provides a command to the second memory chip to enable data transferred in direct to the second memory chip by way of the memory bus in response to a DMA approval signal input.

23. The multichip system as set forth in claim 22, wherein the second memory controller comprises a tri-state buffer that is connected to a pad and conditioned in a floating state in response to the DMA approval signal.

24. The multichip system as set forth in claim 22, wherein the first memory chip comprises:

a memory core storing data;

a first interface unit cooperative to the first memory controller;

a second interface unit cooperative to the second memory chip and the second memory chip;

a control logic unit regulating an operation of the memory core in response to commands input from the first and second interface units; and

a local transfer controller generating the DMA request signal in response to the local transfer information and a local transfer beginning signal input from the control logic unit, and regulating the second interface unit to make data transferred to the second memory chip in response to the DMA approval signal.

25. The multichip system as set forth in claim 24, wherein the local transfer beginning signal is generated when data stored in the memory core are all transferred to the control logic unit in the local transfer mode.

26. The multichip system as set forth in claim 24, wherein the second interface unit comprises a tri-state buffer that is connected to a pad and enabled in response to the DMA approval signal.

27. The multichip system as set forth in claim 22, wherein the first and second memory chips are different in kind.

28. The multichip system as set forth in claim 22, wherein the first memory chip is a nonvolatile memory chip and the second memory chip is a volatile memory chip.

29. The multichip system as set forth in claim 22, wherein the first memory chip is a NAND flash memory chip;

the second memory chip is a DRAM chip;

the first memory controller is a flash memory controller; and

the second memory controller is a DRAM controller.

30. The multichip system as set forth in claim 22, wherein the first memory chip comprises:

a memory core storing data;

a first interface unit cooperative to the first memory controller;

a second interface unit cooperative to the second memory chip and the second memory chip;

a control logic unit regulating an operation of the memory core in response to commands input from the first and second interface units;

a selection circuit activating an alternative one of the first and second interface units in response to a fuse option;

a local transfer controller generating the DMA request signal in response to the local transfer information and a local transfer beginning signal input from the control logic unit, and regulating the second interface unit to make data transferred to the second memory chip in response to the DMA approval signal; and

a tri-state input/output driver connected to the first and second interface units, being enabled in response to the DMA approval signal.

31. The multichip system as set forth in claim 30, wherein the second interface unit comprises a tri-state buffer that is connected to a pad and conditioned on a floating state in response to the DMA approval signal.

32. The multichip system as set forth in claim 30, wherein the first memory chip is a NAND flash memory chip;

the second memory chip is a DRAM chip;

the first interface unit is a NOR flash interface unit; and

the second interface unit is a DRAM interface unit.

33. A method of transferring data in a multichip system including a memory controller, and first and second memory chips, the method comprising the steps of:

(a) providing local transfer information to the first memory chip from the memory controller; and

(b) controlling the second memory chip by the first memory chip to enable data transferred to the second memory chip in response to the local transfer information.

34. The method as set forth in claim 33, wherein the step (b) comprises:

preparing a data transfer in response to the local transfer information; and

confirming whether the data transfer is ready and providing a command to the second memory chip.

35. The method as set forth in claim 33, which further comprises transferring data to the second memory chip from the first memory chip by way of a memory bus connecting the first and second memory chips with each other in direct.

36. The method as set forth in claim 33, wherein the local transfer information contains a local transfer command, source and target addresses, and a data size to be transferred.

37. A method of transferring data in a multichip system including a host system, first and second memory chips, and a memory bus connecting the first and second memory chips to each other in direct, the method comprising the steps of:

(a) supplying local transfer information to the first memory chip from the host system; and

(b) providing a DMA request signal to the host system from the first memory chip in response to the local transfer information, which disables the host system to access the first and second memory chips; and

(c) providing a command to the second memory chip from the first memory chip in response to a DMA approval signal input from the host system, which enables data to be transferred to the second memory chip in direct by way of the memory bus.

38. The method as set forth in claim 37, wherein the step (c) comprises:

preparing a data transfer in response to the local transfer information; and

confirming whether the data transfer is ready and providing the command to the second memory chip.

39. The method as set forth in claim 37, which further comprises transferring data to the second memory chip from the first memory chip by way of the memory bus connecting the first and second memory chips with each other in direct.

40. The method as set forth in claim 37, wherein the local transfer information contains a local transfer command, source and target addresses, and a data size to be transferred.