FORMATION OF SHALLOW JUNCTIONS BY DIFFUSION FROM A DIELECTRIC DOPED BY CLUSTER OR MOLECULAR ION BEAMS
First Claim
1. A process of forming an integrated circuit (IC) containing a metal oxide semiconductor (MOS) transistor further containing lightly doped drain (LDD) diffused regions, comprising the steps of:
- forming an LDD source dielectric layer on a top surface of a well and an MOS gate formed on a top surface of an MOS gate dielectric layer formed on said top surface of said well;
forming an LDD implanted region in a top region of said LDD source dielectric layer by a process of implanting an LDD set of dopant atoms into said LDD source dielectric layer such that less than 10 percent of said LDD dopant atoms pass through said LDD source dielectric layer into said well; and
forming said LDD diffused regions by a process of heating said IC such that a portion of said LDD dopant atoms diffuse from said LDD implanted region into top regions of said well adjacent to said MOS gate.
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Accused Products
Abstract
A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.
65 Citations
43 Claims
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1. A process of forming an integrated circuit (IC) containing a metal oxide semiconductor (MOS) transistor further containing lightly doped drain (LDD) diffused regions, comprising the steps of:
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forming an LDD source dielectric layer on a top surface of a well and an MOS gate formed on a top surface of an MOS gate dielectric layer formed on said top surface of said well; forming an LDD implanted region in a top region of said LDD source dielectric layer by a process of implanting an LDD set of dopant atoms into said LDD source dielectric layer such that less than 10 percent of said LDD dopant atoms pass through said LDD source dielectric layer into said well; and forming said LDD diffused regions by a process of heating said IC such that a portion of said LDD dopant atoms diffuse from said LDD implanted region into top regions of said well adjacent to said MOS gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 43)
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14. A process of forming an IC containing an MOS transistor further containing source and drain (S/D) diffused regions, comprising the steps of:
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forming an S/D source dielectric layer on a top surface of a well, an MOS gate formed on a top surface of an MOS gate dielectric layer formed on said top surface of said well and gate sidewall spacers formed on lateral surfaces of said MOS gate; forming an S/D implanted region in a top region of said S/D source dielectric layer by a process of implanting an S/D set of dopant atoms into said S/D source dielectric layer such that less than 10 percent of said S/D dopant atoms pass through said S/D source dielectric layer into in said well; and forming said S/D diffused regions by a process of heating said IC such that a portion of said S/D dopant atoms diffuse from said S/D implanted region into top regions of said well adjacent to said MOS gate sidewall spacers. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A process of forming an IC containing an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor, comprising the steps of:
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forming an n-type lightly doped drain (NLDD) source dielectric layer on a top surface of a p-well and an NMOS gate formed on a top surface of an NMOS gate dielectric layer formed on said top surface of said p-well; forming an NLDD implanted region in a top region of said NLDD source dielectric layer by a process of implanting an NLDD set of n-type dopant atoms into said NLDD source dielectric layer such that less than 10 percent of said NLDD dopant atoms pass through said NLDD source dielectric layer into said p-well; forming NLDD diffused regions by a process of heating said IC such that a portion of said NLDD dopant atoms diffuse from said NLDD implanted region into top regions of said p-well adjacent to said NMOS gate; forming a p-type lightly doped drain (PLDD) source dielectric layer on a top surface of an n-well and a PMOS gate formed on a top surface of a PMOS gate dielectric layer formed on said top surface of said n-well; forming a PLDD implanted region in a top region of said PLDD source dielectric layer by a process of implanting a PLDD set of p-type dopant atoms into said PLDD source dielectric layer such that less than 10 percent of said PLDD dopant atoms pass through said PLDD source dielectric layer into said n-well; and forming PLDD diffused regions by a process of heating said IC such that a portion of said PLDD dopant atoms diffuse from said PLDD implanted region into top regions of said n-well adjacent to said PMOS gate. - View Dependent Claims (28, 29, 30, 31, 32)
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33. A process of a diffused region in an IC substrate, comprising the steps of:
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forming a source dielectric layer on a top surface of said substrate; forming an implanted region in a top region of said source dielectric layer by a process of implanting a set of dopant atoms into said source dielectric layer such that less than 10 percent of said dopant atoms pass through said source dielectric layer into said substrate; and forming said diffused regions by a process of heating said substrate such that a portion of said dopant atoms diffuse from said implanted region into a top region of said substrate. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42)
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Specification