Methods of Forming a Plurality of Capacitors

• US 20090047769A1
• Filed: 08/13/2007
• Published: 02/19/2009
• Est. Priority Date: 08/13/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhat, Vishwanath, Shea, Kevin R., Good, Farrell
• Granted Patent: US 7,682,924 B2
• Time in Patent Office: Days
• US Class Current: 438/387
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.

Claims

1. A method of forming a plurality of capacitors, comprising:

providing a substrate comprising a capacitor array area, a circuitry area other than the capacitor array area, and an intervening area between the capacitor array area and the circuitry area;

an insulative material received over the capacitor array area and the circuitry area, the capacitor array area comprising a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations, the intervening area comprising a trench within the insulative material;

forming conductive material within the capacitor electrode openings and within the trench to line the capacitor electrode openings and the trench to less than completely fill the trench, the conductive material within the trench and the insulative material of the circuitry area having an elevationally outer interface laterally therebetween;

forming covering material atop the interface and laterally over an upper portion of inner sidewalls of the conductive material within the trench, the covering material not laterally covering an entirety of the inner sidewalls of the conductive material within the trench;

etching the insulative material within the capacitor array area with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the capacitor array area; and

incorporating the conductive material within the capacitor array area into a plurality of capacitors.

2. The method of claim 1 comprising forming the covering material to be non-conformally deposited over the upper portion of the inner sidewalls of the conductive material to have at least two different lateral thicknesses therealong.

3. The method of claim 1 comprising forming the covering material to be of the same composition as that of an elevationally outermost portion of the insulative material.

4. The method of claim 1 comprising forming the covering material to be of different composition from that of an elevationally outermost portion of the insulative material.

5. The method of claim 1 comprising forming the covering material to be insulative.

6. The method of claim 5 comprising forming the covering material to comprise at least one of silicon nitride or undoped silicon dioxide.

7. The method of claim 1 comprising forming the covering material to be conductive.

8. The method of claim 7 comprising forming the covering material to comprise W.

9. The method of claim 1 comprising forming the covering material to be semiconductive.

10. The method of claim 9 comprising forming the covering material to comprise polysilicon.

11. The method of claim 1 comprising forming the covering material to comprise at least one of transparent carbon or amorphous carbon.

12. The method of claim 1 wherein the trench comprises a base, the conductive material being formed to have a portion over and in contact with the trench base, none of said covering material being in contact with said portion of conductive material that is over and in contact with the trench base.

13. The method of claim 1 comprising forming the covering material to a thickness of from about 50 Angstroms to about 1,000 Angstroms over the interface.

14. The method of claim 1 wherein the upper portion of the inner sidewalls over which the covering material is formed is no greater than 20% of depth of the trench within the insulative material.

15. The method of claim 1 wherein the upper portion of the inner sidewalls over which the covering material is formed is no greater than 10% of depth of the trench within the insulative material.

16. The method of claim 1 wherein the liquid etching solution during the etching of the insulative material also etches at least some of the covering material from the substrate.

17. The method of claim 16 wherein the liquid etching solution during the etching of the insulative material etches less than 10% of the covering material from the substrate.

18. The method of claim 16 wherein the liquid etching solution during the etching of the insulative material etches at least a majority of the covering material from the substrate.

19. The method of claim 16 wherein the liquid etching solution etches all of the covering material from the substrate.

20. The method of claim 19 comprising forming the covering material at least in part by chemical vapor depositing Si₃N₄ at a temperature of at least 550°

C., the Si₃N₄ being deposited to a thickness of from about 120 Angstroms to about 200 Angstroms.

21. The method of claim 19 comprising forming the covering material at least in part by chemical vapor depositing Si₃N₄ at a temperature of no greater than 500°

C., the Si₃N₄ being deposited to a thickness of from about 300 Angstroms to about 600 Angstroms.

22. The method of claim 19 wherein all of the insulative material that is etched by the liquid etching solution is etched from the substrate prior to all of the covering material being etched from the substrate.

23. The method of claim 19 wherein all of the covering material is etched from the substrate prior to all of the insulative material that is etched by the liquid etching solution being etched from the substrate.

24. The method of claim 1 wherein the insulative material comprises silicon dioxide comprising at least one of phosphorus and boron, and the liquid etching solution comprises HF.

25. A method of forming a plurality of capacitors, comprising:

providing a substrate comprising a capacitor array area, a circuitry area other than the capacitor array area, and an intervening area between the capacitor array area and the circuitry area;

an insulative material received over the capacitor array area and the circuitry area, the capacitor array area comprising a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations, the intervening area comprising a trench within the insulative material;

forming conductive material within the capacitor electrode openings and within the trench to line the capacitor electrode openings and the trench to less than completely fill the trench, the conductive material within the trench and the insulative material of the circuitry area having an elevationally outer interface laterally therebetween;

forming conductive covering material atop the interface;

etching the insulative material within the capacitor array area and the conductive covering material with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the capacitor array area and to remove all of the conductive covering material from the substrate; and

incorporating the conductive material within the capacitor array area into a plurality of capacitors.

26. The method of claim 25 wherein the conductive covering material is formed laterally over an upper portion of inner sidewalls of the conductive material within the trench.

27. The method of claim 26 wherein the conductive covering material does not laterally cover an entirety of the inner sidewalls of the conductive material within the trench.

28. The method of claim 27 comprising forming the conductive covering material to be non-conformally deposited over the upper portion of the inner sidewalls of the conductive material to have at least two different lateral thicknesses therealong.

29. The method of claim 25 comprising forming the covering material to comprise W.

30. The method of claim 25 wherein the trench comprises a base, the conductive material being formed to have a portion over and in contact with the trench base, none of said conductive covering material being in contact with said portion of conductive material that is over and in contact with the trench base.

31. The method of claim 25 wherein all of the insulative material that is etched by the liquid etching solution is etched from the substrate prior to all of the conductive covering material being etched from the substrate.

32. The method of claim 25 wherein all of the conductive covering material is etched from the substrate prior to all of the insulative material that is etched by the liquid etching solution being etched from the substrate.

33. A method of forming a plurality of capacitors, comprising:

providing a substrate comprising a capacitor array area, a peripheral circuitry area other than the capacitor array area, and an intervening area between the capacitor array area and the peripheral circuitry area;

a doped silicon dioxide material received over the capacitor array area and the peripheral circuitry area, an insulator layer other than doped silicon dioxide received over the doped silicon dioxide material within the capacitor array area and the circuitry area, the capacitor array area comprising a plurality of capacitor electrode openings within the insulator layer and the doped silicon dioxide material which are received over individual capacitor storage node locations, the intervening area comprising a trench within the insulator layer and the doped silicon dioxide material that completely surrounds the capacitor array area;

forming conductive material within the capacitor electrode openings and within the trench to line the capacitor electrode openings and the trench to less than completely fill the capacitor electrode openings and the trench, the conductive material within the trench and the insulator layer of the circuitry area having an elevationally outer interface laterally therebetween;

forming covering material over the insulator layer atop the interface and laterally over an upper portion of inner sidewalls the conductive material within the trench, the covering material not laterally covering an entirety of the inner sidewalls of the conductive material within the trench;

forming etch openings through the covering material and the insulator layer within the capacitor array area effective to expose the doped silicon dioxide material within the capacitor array area while leaving elevationally outermost surfaces of the doped silicon dioxide material within the peripheral circuitry area completely covered with the covering material and the insulator layer;

etching the doped silicon dioxide material within the capacitor array area through the etch openings with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the capacitor array area; and

incorporating the conductive material within the capacitor array area into a plurality of capacitors.

34. The method of claim 33 wherein the liquid etching solution during the etching of the insulator layer also etches at least some of the covering material from the substrate.

35. The method of claim 33 comprising forming the covering material to be non-conformally deposited over the upper portion of the inner sidewalls of the conductive material to have at least two different lateral thicknesses therealong.