Method and Apparatus for Implementing a Multiple Operand Vector Floating Point Summation to Scalar Function

• US 20090049113A1
• Filed: 08/17/2007
• Published: 02/19/2009
• Est. Priority Date: 08/17/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Muff, Adam James, Tubbs, Matthew Ray
• Granted Patent: US 8,239,438 B2
• Time in Patent Office: Days
• US Class Current: 708/524
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3893 controlled in tandem, e.g. multiplier-accumulator

Abstract

Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises computing an arithmetic result of a pair of operands in each processing lane of a vector unit. The arithmetic results generated in each processing lane of the vector unit may be transferred to a dot product unit. The dot product unit may compute an arithmetic result using the arithmetic result computed by each processing lane of the vector unit to generate an arithmetic result of more than two operands.

Claims

1. A method for computing an arithmetic result of more than two operands, comprising:

in response to receiving a multiple operand instruction, computing a first arithmetic result of a pair of operands in each of one or more of a plurality of processing lanes of a vector unit;

transferring the first arithmetic result of each pair of operands from the one or more processing lanes of the vector unit to a dot product unit; and

computing a second arithmetic result, the second arithmetic result being an arithmetic result of each first arithmetic result received from the one or more processing lanes, to generate the arithmetic result of more than two operands.

2. The method of claim 1, wherein the more than two operands are received from one or more registers in a register file.

3. The method of claim 2, wherein each register in the register file comprises a plurality of operands.

4. The method of claim 3, wherein computing the first arithmetic result comprises computing an arithmetic result of a first operand from a first register and a second operand from a second register in a processing lane of the vector unit.

5. The method of claim 1, wherein each vector processing lane comprises an adder configured to calculate the first arithmetic result.

6. The method of claim 1, wherein each processing lane of the vector unit comprises a multiplier, an aligner, and a normalizer.

7. The method of claim 1, wherein the dot product unit comprises an adder configured to compute the second arithmetic result.

8. The method of claim 1, wherein the dot product unit comprises at least one aligner and a normalizer.

9. The method of claim 1, wherein computing the first arithmetic result and the second arithmetic result comprises computing a sum of a first operand and a second operand.

10. The method of claim 1, wherein computing the first arithmetic result and the second arithmetic result comprises computing a difference between a third operand and a fourth operand.

11. A method for computing a sum of eight operands, comprising:

in response to receiving a multiple addend instruction, computing a sum of a pair of operands in each of four processing lanes of a vector unit;

transferring the sum of each pair of operands from each processing lane of the vector unit to a dot product unit; and

adding the sums of each pair of operands in the dot product unit to generate the sum of the eight operands.

12. The method of claim 11, wherein the eight operands are received from one or more registers in a register file, each register in the register file comprising a plurality of operands.

13. The method of claim 12, wherein computing a sum of a pair of operands comprises computing sum of a first operand from a first register and a second operand from a second register in a processing lane of the vector unit.

14. The method of claim 11, wherein each vector processing lane comprises an adder configured to calculate a sum of a pair of operands.

15. The method of claim 11, wherein the dot product unit comprises an adder configured to computer a sum of four operands.

16. A system comprising a plurality of processors communicably coupled with one another, wherein each processor comprises:

a register file comprising a plurality of registers, each register comprising a plurality of operands;

a vector unit comprising a plurality of vector processing lanes and configured to;

receive a multiple operand instruction specifying at least one register; and

in response to receiving the multiple operand instruction, compute a first arithmetic result of a pair of operands received from the at least one register in each of one or more processing lanes of the vector unit; and

a dot product unit configured to receive the first arithmetic result from each of the one or more processing lanes of the vector unit, and compute a second arithmetic result, the second arithmetic result being an arithmetic result of the first arithmetic results received from the one or more processing lanes, to compute an arithmetic result of more than two operands.

17. The system of claim 16, wherein each register of the register file comprises four operands.

18. The system of claim 16, wherein the vector unit is configured to compute the first arithmetic result by computing an arithmetic result of a first operand from a first register and a second operand from a second register in a processing lane of the vector unit.

19. The system of claim 16, wherein each processing lane of the vector unit comprises an adder configured to compute the first arithmetic result.

20. The system of claim 16, wherein each processing lane of the vector unit comprises a multiplier, an aligner, and a normalizer.

21. The system of claim 16, wherein the dot product unit comprises an adder configured to compute the second arithmetic sum.

22. The system of claim 16, wherein the dot product unit comprises at least one aligner and a normalizer.

23. The system of claim 16, wherein computing the first arithmetic result and the second arithmetic result comprises computing a sum of a first operand and a second operand.

24. The system of claim 16, wherein computing the first arithmetic result and the second arithmetic result comprises computing a difference between a third operand and a fourth operand.