INTERRUPT-RELATED CIRCUITS, SYSTEMS, AND PROCESSES

• US 20090049220A1
• Filed: 04/10/2008
• Published: 02/19/2009
• Est. Priority Date: 05/10/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dahan, Franck, Conti, Gregory
• Granted Patent: US 7,934,036 B2
• Time in Patent Office: Days
• US Class Current: 710/267
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic interrupt circuit includes an interrupt-related input line (4235), a security-related status input line (4236), a context-related status input line (4237), and a conversion circuit (4234A) having plural interrupt-related output lines (4245) and selectively operable in response to an interrupt-related signal on said interrupt-related input line (4235) depending on an active or inactive status of each of said security-related status input line (4236) and said context-related status input line (4237).

Claims

1. An electronic interrupt circuit comprising:

an interrupt-related input line;

a security-related status input line;

a context-related status input line; and

a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.

2. The electronic interrupt circuit claimed in claim 1 further comprising a register having a bit field for holding bits related to the state of activity of said plural interrupt-related output lines, a processor circuit, and an interrupt handler circuit coupling said plural interrupt-related output lines to said processor circuit, and said register is coupled separately to said processor circuit.

3. The electronic interrupt circuit claimed in claim 1 further comprising a plurality of enable lines and a logic circuitry having a first set of inputs respectively coupled to the plurality of enable lines and a second set of inputs respectively coupled to said plural interrupt-related output lines.

4. The electronic interrupt circuit claimed in claim 3 wherein said logic circuitry supplies a one-line logic output responsive to both said first set of inputs and said second set of inputs.

5. The electronic interrupt circuit claimed in claim 4 further comprising a reporting register bit coupled to receive said one-line logic output from said logic circuitry.

6. The electronic interrupt circuit claimed in claim 5 further comprising a coupling circuit having an input connected to said one-line logic output from said logic circuitry, said coupling circuit having an interrupt output line.

7. The electronic interrupt circuit claimed in claim 3 wherein said logic circuitry has a set of output lines and includes plural logic gate circuits, each having a first input connected to one of the enable lines and a second input connected to one of the interrupt-related output lines, the logic gate circuits each having an output line forming a different one of the set of output lines of the logic circuitry.

8. The electronic interrupt circuit claimed in claim 7 further comprising a reporting register having a bit field coupled to receive each said output line from said logic gate circuits.

9. A processing system operable in various execution environments comprising:

plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs;

a register coupled to at least one of the processor cores for identifying active execution environments;

a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores; and

a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.

10. The processing system claimed in claim 9 wherein said plural interrupt-related output lines are coupled to provide at least some of the interrupts for routing by said global interrupt handler, and said plural interrupt output lines being at least four times as a numerous as said wait for interrupt outputs.

11. The processing system claimed in claim 9 wherein said conversion circuit is operable to selectively activate a selected one of said plural interrupt output lines depending on an active or inactive status of said security output from a given one of said processor cores and an active or inactive execution environment represented by said register.

12. The processing system claimed in claim 9 wherein said conversion circuit includes a second register configurable by at least one of said processor cores, said second register enabling operations of and recording signal states in said conversion circuit.

13. The processing system claimed in claim 12 further comprising a status update circuit providing an output signal globally signifying a change in any one of at least some of said signal states recorded in said second register.

14. An electronic power management system comprising:

plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output;

a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs; and

a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.

15. The electronic power management system claimed in claim 14 wherein said wait for interrupt expansion circuit is responsive to provide the interrupt signal to a different one of the interrupt inputs depending on which security and context-related mode of a given one of the processors pertains to a wait for interrupt signal therefrom.

16. The electronic power management system claimed in claim 14 further comprising a register, and wherein said wait for interrupt expansion circuit is responsive to the at least one wait for interrupt output to supply a selected portion of said register with a signal representing which of the security and context-related modes of a given one of said processors pertains to a wait for interrupt signal therefrom, said register coupled to at least one of said processors.

17. The electronic power management system claimed in claim 14 further comprising a circuit for routing a system management interrupt from one of the processors to another of said processors.

18. The electronic power management system claimed in claim 14 wherein said processors are operable to run applications and for a first processor to generate a wait for interrupt signal to said wait for interrupt expansion circuit for providing an interrupt signal to a selected one of the interrupt inputs of a second processor among said processors, and for the second processor to transfer at least one application from the first processor onto at least a third processor and then configure said power control circuit to put said first processor into a lower power state.

19. The electronic power management system claimed in claim 14 further comprising a secure state machine having at least one configuration register coupled to said processors and operable for configuring said power control circuit and said wait for interrupt expansion circuit so as to identify any category issuing a wait for interrupt signal from a given processor among said processors even if the given processor becomes powered down by said power control circuit.

20. A processor system with an application and a maintenance function that would interfere with the application if concurrently executed, the processor system comprising

a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output;

a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.

21. The processor system claimed in claim 20 further comprising a memory and wherein each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes memory defragmentation and at least one of said processor cores is operable to launch the memory defragmentation provided an enabling condition exists that any category that uses said memory element is currently in the wait for interrupt mode.

22. The processor system claimed in claim 20 wherein each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes a security integrity check of a secure category on a said processor core, and at least one of said processor cores is operable to launch the security integrity check of that secure category on that processor core provided an enabling condition exists that predetermined public categories are in the wait for interrupt mode.

23. The processor system claimed in claim 20 wherein the processor system is operable to execute plural high-level operating systems (HLOSes), and each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes terminating one HLOS in a particular category on a first of the processor cores and initiating another HLOS on the same processor core, and at least one of said processor cores is operable to launch the other HLOS provided an enabling condition exists that the first processor core activates an interrupt line from the wait for interrupt expansion circuit and signifies that the particular category on the first processor core is in the wait for interrupt mode.

24. An electronic debug circuit comprising

a scan controller operable for serially providing a multi-bit scan signal at a scan output and receiving a multi-bit scan signal at a scan input;

and

a conversion circuit having plural interrupt-related output lines, and said conversion circuit having at least one wait for interrupt input and respective security and context-related signal input lines and said conversion circuit is operable to selectively activate a selected one of said plural interrupt-related output lines depending on active or inactive statuses of said security and context-related input lines; and

a configurable register circuit to enable and record signal states and said configurable register circuit coupled to said conversion circuit, said configurable register circuit coupled to said scan output and to said scan input of said scan controller.

25. A method of operating an electronic circuit having at least one interruptible processor operable in different security and context-related modes and the electronic circuit having a wait for interrupt output, the method comprising expanding the wait for interrupt output depending on which security and context-related modes of a given processor pertain to a wait for interrupt signal therefrom, and providing at least one interrupt signal.

26. A process of manufacturing an electronic product, the process comprising:

preparing in integrated circuitry form an interrupt-related input line, a security related status input line, a virtual context-related status input line and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.

27. A memory comprising:

memory circuitry; and

software stored in the memory circuitry and including at least one interrupt-related instruction specifying an execution environment requesting a service.

28. The memory claimed in claim 27 wherein said interrupt-related instruction includes a system management interrupt instruction defining both an execution environment requesting a service and an execution environment from which the service is requested.

29. The memory claimed in claim 27 wherein said interrupt-related instruction includes a wait for interrupt instruction having an immediate operand.

30. A telecommunications apparatus comprising:

a wireless modem;

a processing system coupled to said wireless modem and including plural processor cores operable in various execution environments and each said core having an interrupt input, a wait for interrupt output, and a security output, and said processing system also including a register coupled to at least one of said cores for identifying active execution environments, and a wait for interrupt expansion circuit fed by said register and a said security output and responsive to provide at least one interrupt signal coupled to at least one said interrupt input in response to at least one said wait for interrupt output; and

a user interface coupled to said processing system.