INTERRUPT-RELATED CIRCUITS, SYSTEMS, AND PROCESSES
First Claim
Patent Images
1. An electronic interrupt circuit comprising:
- an interrupt-related input line;
a security-related status input line;
a context-related status input line; and
a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.
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Abstract
An electronic interrupt circuit includes an interrupt-related input line (4235), a security-related status input line (4236), a context-related status input line (4237), and a conversion circuit (4234A) having plural interrupt-related output lines (4245) and selectively operable in response to an interrupt-related signal on said interrupt-related input line (4235) depending on an active or inactive status of each of said security-related status input line (4236) and said context-related status input line (4237).
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Citations
30 Claims
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1. An electronic interrupt circuit comprising:
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an interrupt-related input line; a security-related status input line; a context-related status input line; and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A processing system operable in various execution environments comprising:
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plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs; a register coupled to at least one of the processor cores for identifying active execution environments; a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores; and a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register. - View Dependent Claims (10, 11, 12, 13)
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14. An electronic power management system comprising:
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plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output; a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs; and a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A processor system with an application and a maintenance function that would interfere with the application if concurrently executed, the processor system comprising
a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output; a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application. - View Dependent Claims (21, 22, 23)
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24. An electronic debug circuit comprising
a scan controller operable for serially providing a multi-bit scan signal at a scan output and receiving a multi-bit scan signal at a scan input; - and
a conversion circuit having plural interrupt-related output lines, and said conversion circuit having at least one wait for interrupt input and respective security and context-related signal input lines and said conversion circuit is operable to selectively activate a selected one of said plural interrupt-related output lines depending on active or inactive statuses of said security and context-related input lines; and a configurable register circuit to enable and record signal states and said configurable register circuit coupled to said conversion circuit, said configurable register circuit coupled to said scan output and to said scan input of said scan controller.
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25. A method of operating an electronic circuit having at least one interruptible processor operable in different security and context-related modes and the electronic circuit having a wait for interrupt output, the method comprising expanding the wait for interrupt output depending on which security and context-related modes of a given processor pertain to a wait for interrupt signal therefrom, and providing at least one interrupt signal.
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26. A process of manufacturing an electronic product, the process comprising:
preparing in integrated circuitry form an interrupt-related input line, a security related status input line, a virtual context-related status input line and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.
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27. A memory comprising:
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memory circuitry; and software stored in the memory circuitry and including at least one interrupt-related instruction specifying an execution environment requesting a service. - View Dependent Claims (28, 29)
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30. A telecommunications apparatus comprising:
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a wireless modem; a processing system coupled to said wireless modem and including plural processor cores operable in various execution environments and each said core having an interrupt input, a wait for interrupt output, and a security output, and said processing system also including a register coupled to at least one of said cores for identifying active execution environments, and a wait for interrupt expansion circuit fed by said register and a said security output and responsive to provide at least one interrupt signal coupled to at least one said interrupt input in response to at least one said wait for interrupt output; and a user interface coupled to said processing system.
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Specification