PCI Express-Compatible Controller And Interface For Flash Memory

• US 20090049222A1
• Filed: 10/20/2008
• Published: 02/19/2009
• Est. Priority Date: 03/17/2004
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Lee, Charles C., Chou, Horng-Yee, See, Sun-Teck, Kao, I-pieng Peter
• Granted Patent: US 7,849,242 B2
• Time in Patent Office: Days
• US Class Current: 710/300
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory

Abstract

A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

Claims

1. A flash memory device for connecting to a PCI Express-defined bus, the flash memory device comprising:

a flash memory module for storing data;

a connector for connecting to the PCI Express-defined bus, thereby allowing packets to be transmitted between the PCI Express-defined bus and the flash memory device; and

a flash controller for controlling the flash memory module and the connector.

2. The flash memory device of claim 1, wherein the connector is an ExpressCard connector.

3. The flash memory device of claim 1, wherein the flash controller includes an analog end unit.

4. The flash memory device of claim 3, wherein the analog end unit can perform at least one of serial to parallel signal conversion, differential signaling, and phase locking.

5. The flash memory device of claim 3, wherein the flash controller includes a physical interface engine for extracting transaction layer packet (TLP) information from a signal output by the analog end unit.

6. The flash memory device of claim 5, wherein the physical interface engine can perform at least one of packet framing/de-framing, 8-bit to 10-bit encoding/decoding, and packet scrambling/de-scrambling.

7. The flash memory device of claim 5, further including a command register for receiving the extracted TLP.

8. A flash memory device comprising:

flash memory mappable to an address space of a host that is separate from the flash memory device;

a PCI Express-defined connector for allowing the host to communicate with the flash memory device; and

a PCI Express-compatible controller supporting this communication using a command word setting.

9. The flash memory device of claim 8, wherein the PCI Express-defined connector is an ExpressCard connector.

10. The flash memory device of claim 8, wherein the PCI Express-compatible controller extracts transaction layer packets (TLPs) from a signal from the host.

11. The flash memory device of claim 10, wherein each TLP includes at least one of a header, a data payload, and a digest.

12. The flash memory device of claim 11, wherein the data payload can provide the command word setting, and wherein the PCI Express-compatible controller can respond to the command word setting.

13. The flash memory device of claim 12, wherein the command word setting includes a command word signature indicating whether the data payload is one of data and the command word setting.

14. The flash memory device of claim 13, wherein the command word setting includes a data unit transfer length.

15. The flash memory device of claim 14, wherein the command word setting includes an operation code designating an operation to be performed on the flash memory.

16. The flash memory device of claim 15, wherein the command word setting includes a logical block address indicating a starting location in the flash memory for the operation.

17. The flash memory device of claim 16, wherein the command word setting includes a data transfer length based on the data unit transfer length.

18. The flash memory device of claim 12, wherein the command word setting can indicate an operation to be performed on the flash memory.

19. The flash memory device of claim 18, wherein the operation can include one of a flash memory read, a flash memory write, a flash memory erase, a direct memory access read, and a direct memory access write.

20. The flash memory device of claim 12, wherein the command word setting can indicate an operation to be performed on a register of the flash memory device.

21. The flash memory device of claim 20, wherein the operation can include one of an attribute register read, an attribute register write, and a status register read.

22. The flash memory device of claim 12, wherein the command word setting can indicate an operation to be performed on the flash memory device.

23. The flash memory device of claim 22, wherein the operation can include a device reset.

24. A transaction layer packet (TLP) compatible with PCI Express, the TLP comprising:

a header field; and

a data payload field, wherein the data payload field can include a command word setting relating to an operation to be performed on a flash memory.

25. The TLP of claim 24, wherein the command word setting includes a command word signature indicating whether the data payload includes one of data and the command word setting.

26. The TLP of claim 25, wherein the command word setting includes a data unit transfer length.

27. The TLP of claim 26, wherein the command word setting includes an operation code designating an operation to be performed using the flash memory.

28. The TLP of claim 27, wherein the command word setting includes a logical block address indicating a starting location in the flash memory for the operation.

29. The TLP of claim 28, wherein the command word setting includes a data transfer length based on the data unit transfer length.

30. The TLP of claim 24, wherein the command word setting can indicate an operation to be performed on the flash memory.

31. The TLP of claim 30, wherein the operation can include one of a flash memory read, a flash memory write, a flash memory erase, a direct memory access read, and a direct memory access write.

32. The TLP of claim 24, wherein the command word setting can indicate an operation to be performed on a register of the flash memory device.

33. The TLP of claim 24, wherein the command word setting can indicate an operation to be performed on a plurality of registers of the flash memory device.

34. The TLP of claim 32, wherein the operation can include one of an attribute register read, an attribute register write, and a status register read.

35. The TLP of claim 24, wherein the command word setting can indicate an operation to be performed using the flash memory device.

36. The TLP of claim 35, wherein the operation can include a device reset.