CIRCUITS WITH TRANSIENT ISOLATION OPERABLE IN A LOW POWER STATE

• US 20090049321A1
• Filed: 08/15/2007
• Published: 02/19/2009
• Est. Priority Date: 08/15/2007
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Leung, Charles, Voleti, Siva Raghu Ram, Balatsos, Aris
• Granted Patent: US 7,904,838 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An integrated circuit suitable for power conservation is disclosed. The circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.

Claims

1. An integrated circuit comprising:

a core-logic providing a core-logic output;

an isolation circuit in communication with said core-logic, operable to selectively provide an output corresponding to one of said core-logic output and a predetermined value;

a latch interconnected to said isolation circuit, receiving said output of said isolation circuit;

a power consumption controller in communication with said core-logic, said latch and said isolation circuit, said controller operable to;

control said latch to store a value of said core-logic output and provide a corresponding output;

control said isolation circuit to provide an output corresponding to said predetermined value, at said output of said isolation circuit; and

transition said core-logic from a high power state to a low power state.

2. The circuit of claim 1, wherein said controller is further operable to:

transition said core-logic from said low power state to said high power state;

control said isolation circuit to provide an output corresponding to said core-logic output of said core-logic in said high power state; and

control said latch to provide an output corresponding to said output of said isolation circuit.

3. The circuit of claim 2, wherein said controller is further operable to initialize said core-logic prior to controlling said latch to provide said output corresponding to said output of said isolation circuit, while said core-logic is in said high power state.

4. The circuit of claim 1, wherein said core-logic comprises at least one power-island providing said core-logic output to an input of said isolation cell, and wherein said controller disconnects power to said at least one power-island to transition said core-logic from said high power state to said low power state.

5. The circuit of claim 4, wherein said core-logic comprises a second power-island having an input receiving said output of said isolation cell.

6. The circuit of claim 1, further comprising a plurality of I/O pads wherein one of said I/O pads is interconnected to an output of said latch.

7. The circuit of claim 1, wherein said isolation circuit comprises one of an AND-gate, an OR-gate, a NOR gate, and a NAND gate.

8. The circuit of claim 7, wherein said latch comprises a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor.

9. The circuit of claim 5, wherein while said core-logic is in said low power state, said second power-island remains powered and fully operational.

10. The circuit of claim 5, wherein said core-logic further comprises a plurality of power-islands interconnected with corresponding ones of a plurality of power control switches, each of said switches selectively providing power to a corresponding one of said power-islands.

11. A graphics processor comprising the circuit of claim 6.

12. A computing device comprising the graphics processor of claim 11.

13. The computing device of claim 12, wherein said computing device is a handheld device comprising a display.

14. A dynamic random access memory (DRAM) controller comprising the circuit of claim 1.

15. A method of operating an integrated circuit comprising a core-logic providing a core-logic output to an isolation circuit operable to selectively provide an output corresponding to one of said core-logic output and a predetermined value, to an input of a latch interconnected with an output of said isolation circuit;

said method comprising;

signaling said latch to store a value of said output of said isolation circuit corresponding to said core-logic output, and provide a corresponding output;

signaling said isolation circuit to provide an output corresponding to said predetermined value; and

removing power supplied to at least a portion of said core-logic, thereby placing said integrated circuit in a low power state.

16. The method of claim 15, wherein said removing is performed under control of a power consumption controller.

17. The method of claim 15, further comprising:

supplying power to said at least a portion of said core-logic;

signaling said isolation circuit to provide an output corresponding to said core-logic output to said input of said latch; and

signaling said latch to provide an output corresponding to said output of said isolation circuit.

18. The method of claim 17, further comprising initializing said core-logic prior to said signaling said latch.

19. The method of claim 17, wherein said supplying is performed by a power consumption controller.

20. The method of claim 17, wherein said portion of said core-logic comprises a power-island and wherein said removing power comprises selectively disconnecting power from said power-island.

21. An integrated circuit comprising a controller in communication with an isolation circuit and a latch;

said isolation circuit comprising a first input, a second input and an output for selectively providing an output signal corresponding to an input signal received at said first input or a predetermined signal value, in response to a signal received at said second input;

said latch comprising a data input interconnected to said output of said isolation circuit for receiving a data signal, a control input for receiving a control signal and an output;

said controller operable to;

assert said control signal to control said latch to store a value of said data signal, and output a corresponding signal; and

signal said isolation circuit to provide an output signal corresponding to said predetermined signal value.

22. The circuit of claim 21, wherein said controller is further operable to:

signal said isolation circuit to provide an output signal corresponding to said input signal received at said first input.

de-assert said control signal to control said latch to provide an output corresponding to said data signal.

23. The circuit of claim 21, wherein said isolation circuit is an AND-gate.

24. The circuit of claim 21, wherein said isolation circuit is an OR-gate.

25. The circuit of claim 23, wherein said gate comprises CMOS transistors.