Semiconductor device

• US 20090050941A1
• Filed: 08/19/2008
• Published: 02/26/2009
• Est. Priority Date: 08/24/2007
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuma, Hideto, Kakehata, Tetsuya, Yamazaki, Shunpei
• Application Number:
  US12/222,917
• Publication Number:
  US 20090050941A1
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.

Claims

1. A semiconductor device comprising:

an insulating substrate;

a first field-effect transistor over the insulating substrate, the first field-effect transistor comprising;

a first single-crystalline semiconductor layer;

a first gate insulating layer; and

a first gate electrode layer;

a planarization layer over the first field-effect transistor; and

a second field-effect transistor over the planarization layer, the second field-effect transistor comprising;

a second single-crystalline semiconductor layer;

a second gate insulating layer; and

a second gate electrode layer.

2. The semiconductor device according to claim 1,

wherein a conductivity type of the first field-effect transistor is an n-type and a conductivity type of the second field-effect transistor is a p-type.

3. The semiconductor device according to claim 1,

wherein a crystal plane orientation of a plane of the first single-crystalline semiconductor layer is a {100} plane and a crystal plane orientation of a plane of the second semiconductor layer is a {110} plane.

4. The semiconductor device according to claim 3,

wherein a crystal axis of a channel length direction of the first single-crystalline semiconductor layer is <

100> and

a crystal axis of a channel length direction of the second single-crystalline semiconductor layer is <

110>

.

5. The semiconductor device according to claim 1,

wherein the first single-crystalline semiconductor layer and the second single-crystalline semiconductor layer are overlapped with each other with the planarization layer interposed therebetween, and

the first field-effect transistor and the second field-effect transistor are electrically connected to each other by a wiring which is formed in an opening which penetrates the second single-crystalline semiconductor layer, the planarization layer, and the first gate insulating layer and reaches the first single-crystalline semiconductor layer.

6. The semiconductor device according to claim 1,

wherein the insulating substrate is a glass substrate.

7. A semiconductor device comprising:

an insulating substrate;

a first insulating layer over the insulating substrate;

a first field-effect transistor over the first insulating layer, the first field-effect transistor comprising;

a first single-crystalline semiconductor layer;

a first gate insulating layer; and

a first gate electrode layer;

a planarization layer over the first field-effect transistor;

a second insulating layer over the planarization layer; and

a second field-effect transistor over the second insulating layer, the second field-effect transistor comprising;

a second single-crystalline semiconductor layer;

a second gate insulating layer; and

a second gate electrode layer.

8. The semiconductor device according to claim 7,

wherein a conductivity type of the first field-effect transistor is an n-type and a conductivity type of the second field-effect transistor is a p-type.

9. The semiconductor device according to claim 7,

wherein a crystal plane orientation of a plane of the first single-crystalline semiconductor layer is a {100} plane and a crystal plane orientation of a plane of the second semiconductor layer is a {110} plane.

10. The semiconductor device according to claim 9,

wherein a crystal axis of a channel length direction of the first single-crystalline semiconductor layer is <

100> and

a crystal axis of a channel length direction of the second single-crystalline semiconductor layer is <

110>

.

11. The semiconductor device according to claim 7,

wherein the first single-crystalline semiconductor layer and the second single-crystalline semiconductor layer are overlapped with each other with the planarization layer interposed therebetween, and

the first field-effect transistor and the second field-effect transistor are electrically connected to each other by a wiring which is formed in an opening which penetrates the second single-crystalline semiconductor layer, the planarization layer, and the first gate insulating layer and reaches the first single-crystalline semiconductor layer.

12. The semiconductor device according to claim 7,

wherein the insulating substrate is a glass substrate.

13. A semiconductor device comprising:

an insulating substrate;

a first field-effect transistor over the insulating substrate, the first field-effect transistor comprising;

a first single-crystalline semiconductor layer;

a first gate insulating layer; and

a first gate electrode layer;

a planarization layer over the first field-effect transistor; and

a second field-effect transistor over the planarization layer, the second field-effect transistor comprising;

a second single-crystalline semiconductor layer;

a second gate insulating layer; and

a second gate electrode layer,

wherein a crystal plane orientation of the first single-crystalline semiconductor layer and a crystal plane orientation of the second single-crystalline semiconductor layer are different from each other.

14. The semiconductor device according to claim 13,

wherein a conductivity type of the first field-effect transistor is an n-type and a conductivity type of the second field-effect transistor is a p-type.

15. The semiconductor device according to claim 13,

wherein the crystal plane orientation of the first single-crystalline semiconductor layer is a {100} plane and the crystal plane orientation of the second semiconductor layer is a {110} plane.

16. The semiconductor device according to claim 15,

wherein a crystal axis of a channel length direction of the first single-crystalline semiconductor layer is <

100> and

a crystal axis of a channel length direction of the second single-crystalline semiconductor layer is <

110>

.

17. The semiconductor device according to claim 13,

wherein the first single-crystalline semiconductor layer and the second single-crystalline semiconductor layer are overlapped with each other with the planarization layer interposed therebetween, and

the first field-effect transistor and the second field-effect transistor are electrically connected to each other by a wiring which is formed in an opening which penetrates the second single-crystalline semiconductor layer, the planarization layer, and the first gate insulating layer and reaches the first single-crystalline semiconductor layer.

18. The semiconductor device according to claim 13,

wherein the insulating substrate is a glass substrate.

19. A semiconductor device comprising:

an insulating substrate;

a first field-effect transistor over the insulating substrate, the first field-effect transistor comprising;

a first single-crystalline semiconductor layer;

a first gate insulating layer; and

a first gate electrode layer;

a planarization layer over the first field-effect transistor; and

a second field-effect transistor over the planarization layer, the second field-effect transistor comprising;

a second single-crystalline semiconductor layer;

a second gate insulating layer; and

a second gate electrode layer,

wherein a crystal plane orientation of the first single-crystalline semiconductor layer and a crystal plane orientation of the second single-crystalline semiconductor layer are same, and

wherein a crystal axis of a channel length direction of the first single-crystalline semiconductor layer and a crystal axis of a channel length direction of the second single-crystalline semiconductor layer are different from each other.

20. The semiconductor device according to claim 19,

wherein a conductivity type of the first field-effect transistor is an n-type and a conductivity type of the second field-effect transistor is a p-type.

21. The semiconductor device according to claim 19,

wherein the crystal plane orientations of the first single-crystalline semiconductor layer and the second semiconductor layer are {100} planes.

22. The semiconductor device according to claim 21,

wherein a crystal axis of a channel length direction of the first single-crystalline semiconductor layer is <

100> and

a crystal axis of a channel length direction of the second single-crystalline semiconductor layer is <

110>

.

23. The semiconductor device according to claim 19,

wherein the first single-crystalline semiconductor layer and the second single-crystalline semiconductor layer are overlapped with each other with the planarization layer interposed therebetween, and

the first field-effect transistor and the second field-effect transistor are electrically connected to each other by a wiring which is formed in an opening which penetrates the second single-crystalline semiconductor layer, the planarization layer, and the first gate insulating layer and reaches the first single-crystalline semiconductor layer.

24. The semiconductor device according to claim 19,

wherein the insulating substrate is a glass substrate.

25. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first fragile layer in a first single-crystalline semiconductor substrate by ion irradiation;

bonding the first single-crystalline semiconductor substrate over an insulating substrate;

separating the first single-crystalline semiconductor substrate at the first fragile layer so that a first single-crystalline semiconductor layer is formed over the insulating substrate;

forming a first field-effect transistor using the first single-crystalline semiconductor layer;

forming a planarization layer over the first field-effect transistor;

forming a second fragile layer in a second single-crystalline semiconductor substrate by ion irradiation;

bonding the second single-crystalline semiconductor substrate over the planarization layer;

separating the second single-crystalline semiconductor substrate at the second fragile layer so that a second single-crystalline semiconductor layer is formed over the planarization layer; and

forming a second field-effect transistor using the single-crystalline second semiconductor layer.

26. The method for manufacturing a semiconductor device according to claim 25,

wherein a conductivity type of the first field-effect transistor is an n-type and a conductivity type of the second field-effect transistor is a p-type.

27. The method for manufacturing a semiconductor device according to claim 25,

wherein a crystal plane orientation of a plane of the first single-crystalline semiconductor layer is a {100} plane and a crystal plane orientation of a plane of the second semiconductor layer is a {110} plane.

28. The method for manufacturing a semiconductor device according to claim 27,

wherein a crystal axis of a channel length direction of the first single-crystalline semiconductor layer is <

100> and

a crystal axis of a channel length direction of the second single-crystalline semiconductor layer is <

110>

.

29. The method for manufacturing a semiconductor device according to claim 25,

wherein the first single-crystalline semiconductor layer and the second single-crystalline semiconductor layer are overlapped with each other with the planarization layer interposed therebetween, and

the first field-effect transistor and the second field-effect transistor are electrically connected to each other by a wiring which is formed in an opening which penetrates the second single-crystalline semiconductor layer, the planarization layer, and the first gate insulating layer and reaches the first single-crystalline semiconductor layer.

30. The method for manufacturing a semiconductor device according to claim 25,

wherein the insulating substrate is a glass substrate.