NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20090050953A1
• Filed: 08/22/2007
• Published: 02/26/2009
• Est. Priority Date: 08/22/2007
• Status: Abandoned Application

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Wang, Szu-Yu, Lue, Hang-Ting
• Application Number:
  US11/842,990
• Publication Number:
  US 20090050953A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A non-volatile memory device including a substrate, an insulating layer, a charge storage layer, a multi-layer tunneling dielectric structure and a gate is provided. The substrate has a channel region. The insulating layer is disposed on the channel region. The charge storage layer is disposed on the insulating layer. The multi-layer tunneling dielectric structure is disposed on the charge storage layer. The gate is disposed on the multi-layer tunneling dielectric structure and the charge carriers are injected from the gate.

Claims

1. A non-volatile memory device, comprising:

a substrate comprising a channel region;

an insulating layer disposed on the channel region;

a charge storage layer disposed on the insulating layer;

a multi-layer tunneling dielectric structure disposed on the charge storage layer; and

a gate disposed on the multi-layer tunneling dielectric structure.

2. The non-volatile memory device according to claim 1, wherein the multi-layer tunneling dielectric structure comprises a third dielectric layer, a second dielectric layer and a first dielectric layer, the third dielectric layer is disposed on the charge storage layer, the second dielectric layer is disposed on the third dielectric layer, the first dielectric layer is disposed on the second dielectric layer, and at least the second dielectric layer contains nitrogen (N).

3. The non-volatile memory device according to claim 2, wherein the third dielectric layer, the second dielectric layer and the first dielectric layer consist essentially of silicon (Si), nitrogen (N) and oxygen (O).

4. The non-volatile memory device according to claim 3, wherein the conductive energy band level (Ec) of at least one region of the second dielectric layer is higher than that of the third dielectric layer and the first dielectric layer, and the valence energy band level (Ev) of the at least one region is lower than that of the third dielectric layer and the first dielectric layer.

5. The non-volatile memory device according to claim 3, wherein the nitrogen concentration of at least one region of the second dielectric layer is higher than that of the third dielectric layer and the first dielectric layer.

6. The non-volatile memory device according to claim 2, wherein the third dielectric layer, the second dielectric layer and the first dielectric layer respectively are made from oxide, nitride and oxide.

7. The non-volatile memory device according to claim 2, wherein the third dielectric layer, the second dielectric layer and the first dielectric layer are respectively made from silicon oxide, silicon nitride and silicon oxide.

8. The non-volatile memory device according to claim 2, wherein the third dielectric layer, the second dielectric layer and the first dielectric layer are respectively made form silicon oxide, aluminum oxide and silicon oxide.

9. The non-volatile memory device according to claim 2, wherein thickness of the first dielectric layer is less than 20 angstroms (Å

).

10. The non-volatile memory device according to claim 2, wherein thickness of the first dielectric layer ranges between 5 Å

-20 Å

.

11. The non-volatile memory device according to claim 2, wherein thickness of the first dielectric layer is less than 15 Å

.

12. The non-volatile memory device according to claim 2, wherein thickness of the second dielectric layer is less than 20 Å

.

13. The non-volatile memory device according to claim 2, wherein thickness of the second dielectric layer ranges between 10 Å

-20 Å

.

14. The non-volatile memory device according to claim 2, wherein thickness of the third dielectric layer is less than 20 Å

.

15. The non-volatile memory device according to claim 2, wherein thickness of the third dielectric layer ranges between 15 Å

-20 Å

.

16. The non-volatile memory device according to claim 1, wherein the charge storage layer is made from silicon nitride, silicon oxynitride, hafnium oxide or aluminum oxide.

17. The non-volatile memory device according to claim 1, wherein the insulating layer on channel region is made from silicon nitride or silicon oxynitride.

18. The non-volatile memory device according to claim 1, wherein the insulating layer on channel region is made from hafnium oxide or aluminum oxide.

19. The non-volatile memory device according to claim 1, wherein the substrate further comprises a source region and a drain region, the source region and the drain region are interspaced by the channel region.

20. The non-volatile memory device according to claim 1, wherein the insulating layer is made from silicon oxide or silicon oxynitride.

21. The non-volatile memory device according to claim 1, wherein the gate is made from metal, polycrystalline silicon, metal silicide or a combination thereof.

22. The non-volatile memory device according to claim 1, wherein the multi-layer tunneling dielectric structure comprises a second dielectric layer and a first dielectric layer, the second dielectric layer is disposed on the charge storage layer, the first dielectric layer is disposed on the second dielectric layer, and at least the second dielectric layer contains nitrogen.

23. A manufacturing method of a non-volatile memory device, the method comprising:

(a) forming an insulating material layer on a substrate;

(b) forming a charge storage material layer on the insulating material layer;

(c) forming a multi-layer tunneling dielectric material on the charge storage material layer;

(d) forming a gate material layer on the multi-layer tunneling dielectric material;

(e) forming a patterned photo-resist layer on the gate material layer; and

(f) etching the insulating material layer, the charge storage material layer, the multi-layer tunneling dielectric material and the gate material layer according to the patterned photo-resist layer to form a memory structure.

24. The manufacturing method according to claim 23, wherein the step (c) further comprises:

(c1) forming a third dielectric layer on the charge storage material layer;

(c2) forming a second dielectric material layer on the third dielectric layer, wherein the second dielectric material layer contains nitrogen; and

(c3) forming a first dieletric material layer on the second dielectric material layer.

25. The manufacturing method according to claim 24, wherein the step (c1) further comprises:

depositing a silicide material on the charge storage material layer.

26. The manufacturing method according to claim 25, wherein after the step of depositing the silicide material, the method further comprises:

oxidizing the silicide material.

27. The manufacturing method according to claim 25, wherein the step (c2) further comprises:

depositing a silicide material on the third dielectric layer.

28. The manufacturing method according to claim 27, wherein after the step of depositing the silicide material, the method further comprises:

nitridizing the silicide material.

29. The manufacturing method according to claim 24, wherein the step (c3) further comprises:

depositing a silicide material on the second dielectric material layer.

30. The manufacturing method according to claim 29, wherein after the step of depositing the silicide material, the method further comprises:

oxidizing the silicide material.

31. The manufacturing method according to claim 23, wherein the step (a) further comprises:

depositing a silicide material on the substrate.

32. The manufacturing method according to claim 31, wherein after the step of depositing the silicide material, the method further comprises:

oxidizing the silicide material.

33. The manufacturing method according to claim 23, wherein the step (b) further comprises:

depositing a silicide material on the insulating material layer.

34. The manufacturing method according to claim 33, wherein after the step of depositing the silicide material, the method further comprises:

nitridizing the silicide material.

35. The manufacturing method according to claim 23, wherein between the step (d) and the step (e), the method further comprises:

implanting ions to the gate material layer.

36. The manufacturing method according to claim 23, wherein after the step (f), the method further comprises:

implanting ions to the substrate to form a source region, a drain region and a channel region, wherein the source region and the drain region are interspaced by the channel region.

37. The manufacturing method according to claim 23, further comprising a thermal nitridation process in NO, N₂O, NH₃, or ND₃ can be performed either before or after the insulating layer formation.

38. The manufacturing method according to claim 23, further comprising a plasma nitridation process can be performed either before or after the insulating layer formation.