SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20090050956A1
• Filed: 08/14/2008
• Published: 02/26/2009
• Est. Priority Date: 08/24/2007
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: ISHIMARU, TETSUYA, MINE, TOSHIYUKI, KAWASHIMA, YOSHIYUKI, SHIMAMOTO, YASUHIRO, YASUI, KAN, ARIGANE, TSUYOSHI
• Application Number:
  US12/191,958
• Publication Number:
  US 20090050956A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed thicker than that of the gate dielectric under the gate longitudinal direction center and the thickness of the lower layer dielectric film that is positioned between the select gate electrode and the charge storage layer and is nearest to a semiconductor substrate is formed 1.5 times or below of the thickness of the lower layer dielectric film positioned between the semiconductor substrate and the charge storage layer.

Claims

1. A semiconductor memory device comprising nonvolatile memory cells including a first field effect transistor in a first region of the main surface of a semiconductor substrate, and a second field effect transistor which is adjacent to the first field effect transistor in a second region, wherein

a first gate electrode of the first field effect transistor formed in the first region, a second gate electrode of the second field effect transistor formed in the second region, a first gate dielectric formed between the semiconductor substrate and the first gate electrode, a charge storage layer formed between the semiconductor substrate and the second gate electrode and between the first gate electrode and the second gate electrode, and a first dielectric film formed between the semiconductor substrate and the charge storage layer and between the first gate electrode and the charge storage layer are arranged,

the thickness of the first gate dielectric under the gate longitudinal direction end of the first gate electrode is thicker than that of the first gate dielectric under the gate longitudinal direction center of the first gate electrode, and the thickness of the first dielectric film that is positioned between the first gate electrode and the charge storage layer and is nearest to the semiconductor substrate, is 1.5 times or below of the thickness of the first dielectric film between the semiconductor substrate and the charge storage layer.

2. The semiconductor memory device according to claim 1, wherein the thickness of the first gate dielectric under the gate longitudinal direction end of the first gate electrode is thicker by 0.5 nm or more than that of the first gate dielectric under the gate longitudinal direction center of the first gate electrode.

3. The semiconductor memory device according to claim 1, further comprising

a third field effect transistor formed in a third region of the main surface of the semiconductor substrate for performing a logic operation,

a third gate electrode of the third field effect transistor formed in the third region, and

a second gate dielectric formed between the semiconductor substrate and the third gate electrode are arranged, and wherein

the difference between the thickness of the second gate dielectric under the gate longitudinal direction end of the third gate electrode and the thickness of the second gate dielectric under the gate longitudinal direction center of the third above gate electrode is 0.5 nm or below.

4. The semiconductor memory device according to claim 1, wherein the thickness of the first gate dielectric under one gate longitudinal direction end of the first gate electrode is thicker than that of the first gate dielectric under the gate longitudinal direction center of the first gate electrode.

5. The semiconductor memory device according to claim 1, wherein the charge storage layer is a silicon nitride film, an silicon oxynitride film, a tantalum oxide film or an aluminum oxide film.

6. The semiconductor memory device according to claim 1, wherein the first dielectric film is a silicon oxide film.

7. The semiconductor memory device according to claim 1, wherein a second dielectric film is arranged between the second gate electrode and the charge storage layer.

8. The semiconductor memory device according to claim 7, wherein the second dielectric film is a silicon oxide film, a dielectric film in which a silicon nitride film is inserted in between silicon oxide films, or a dielectric film in which an amorphous silicon film is inserted in between silicon oxide films.

9. The semiconductor memory device according to claim 1, wherein information is written by injecting hot electrons into the charge storage layer by an SSI method.

10. The semiconductor memory device according to claim 1, wherein information is erased by injecting hot holes into the charge storage layer by a BTBT phenomenon.

11. A method of manufacturing a semiconductor memory device for forming nonvolatile memory cells including a first field effect transistor in a first region of the main surface of a semiconductor substrate, and a second field effect transistor which is adjacent to the first field effect transistor in a second region, the method comprising the steps of:

(a) forming a first gate dielectric in the main surface of the semiconductor substrate in the first region;

(b) forming the first gate electrode of the first field effect transistor comprising the first conductive film via the first gate dielectric in the first region, after forming the first conductive film on the main surface of the semiconductor substrate;

(c) removing the first gate dielectric of other regions than the first gate dielectric under the first gate electrode;

(d) performing a first oxidation processing to the semiconductor substrate, and making the thickness of the first gate dielectric under the gate longitudinal direction end of the first gate electrode thicker than that of the first gate dielectric under the gate longitudinal direction center of the first gate electrode;

(e) performing a second oxidation processing to the semiconductor substrate by removing the whole or part of an oxide film formed by the first oxidation processing, after the step (d), and thereby forming a first dielectric film;

(f) forming a charge storage layer on the first dielectric film, after the step (e);

(g) forming the second conductive film on the main surface of the semiconductor substrate after the step (f), processing the second conductive film by anisotropic etching, and thereby forming sidewalls comprising the second conductive films on both of the sides of the first gate electrode;

(h) removing the sidewall formed on one side of the first gate electrode, and making the sidewall remaining on the other side of the first gate electrode a second gate electrode; and

(i) removing the first dielectric film and the charge storage layer of other regions than the first dielectric film and the charge storage layer formed between the first gate electrode and the second gate electrode, and in a second region.

12. The method of manufacturing a semiconductor memory device according to claim 11, wherein, in the step (e), the first dielectric film is formed so that the thickness of the first dielectric film that is positioned between the first gate electrode and the charge storage layer and is nearest to the semiconductor substrate, is 1.5 times or below of that of the first dielectric film between the semiconductor substrate and the charge storage layer.

13. The method of manufacturing a semiconductor memory device according to claim 11, wherein the thickness of the first gate dielectric under the gate longitudinal direction end of the first gate electrode is formed thicker by 0.5 nm or more than that of the first gate dielectric under the gate longitudinal direction center of the first gate electrode.

14. The method of manufacturing a semiconductor memory device according to claim 11, further comprising the following step between the step (f) and the step (g):

(j) forming a second dielectric film on the charge storage layer.

15. The method of manufacturing a semiconductor memory device according to claim 11, wherein the second oxidation processing is performed to the semiconductor substrate by performing ISSG oxidation processing.

16. The method of manufacturing a semiconductor memory device according to claim 11, wherein the first oxidation processing is wet oxidation processing.

17. The method of manufacturing a semiconductor memory device according to claim 11, wherein the first oxidation processing is dry oxidation processing.

18. The method of manufacturing a semiconductor memory device according to claim 17, wherein, in the step (c), the first gate dielectric under the gate longitudinal direction end of the first gate electrode is further etched by 3 to 20 nm from the end of the first gate electrode.

19. The method of manufacturing a semiconductor memory device according to claim 11, wherein the step (d) further including the steps of:

(d1) forming a third dielectric film on the main surface of the semiconductor substrate;

(d2) forming sidewalls comprising a fourth dielectric film via the third dielectric film on the sides of the first gate electrode;

(d3) removing the third dielectric film, until the first gate dielectric under the first gate electrode is exposed; and

(d4) performing dry oxidation processing to the semiconductor substrate, and forming the thickness of the first gate dielectric under the gate longitudinal direction end of the first gate electrode thicker than that of the first gate dielectric under the gate longitudinal direction center of the first gate electrode, and further,

the step (e) including a step of

(e1) removing the third dielectric film of other regions than the first gate dielectric under the first gate electrode, the sidewalls, and the oxide film formed by the dry oxidation processing.