Method and Structure for Shielded Gate Trench FET

• US 20090050959A1
• Filed: 08/30/2007
• Published: 02/26/2009
• Est. Priority Date: 08/21/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Madson, Gordon K.
• Granted Patent: US 8,497,549 B2
• Time in Patent Office: Days
• US Class Current: 257/332
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.

Claims

1. A shielded gate field effect transistor, comprising:

a trench extending into a semiconductor region;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric which comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region, the second dielectric layer comprising a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer;

an inter-electrode dielectric overlying the shield electrode;

a gate dielectric lining upper trench sidewalls; and

a gate electrode in an upper portion of the trench over the inter-electrode dielectric.

2. The shielded gate field effect transistor of claim 1 wherein the first dielectric layer extends along the trench sidewalls, portions of the first dielectric layer extending along upper trench sidewalls forming the gate dielectric.

3. The shielded gate field effect transistor of claim 2 wherein the first dielectric layer comprises an oxide layer and the second dielectric layer comprises a silicon nitride layer.

4. The shielded gate field effect transistor of claim 1 wherein the first and second dielectric layers extend along the trench sidewalls, portions of the first and second dielectric layer extending along upper trench sidewalls forming the gate dielectric.

5. The shielded gate field effect transistor of claim 4 wherein the first dielectric layer comprises an oxide layer and the second dielectric layer comprises a silicon nitride layer.

6. The shielded gate field effect transistor of claim 1 wherein the first dielectric layer comprises an oxide layer, the second dielectric layer comprises a silicon nitride layer, and the gate dielectric comprises a gate oxide layer.

7. The shielded gate field effect transistor of claim 6 wherein the gate dielectric further comprises a silicon nitride layer.

8. The shielded gate field effect transistor of claim 1 wherein the semiconductor region comprises:

a drift region of a first conductivity type;

a body region of a second conductivity type extending over the drift region; and

source regions of the first conductivity type in the body region adjacent to the trench.

9. The shielded gate field effect transistor of claim 8 wherein the gate electrode is recessed in the trench to below a top surface of the semiconductor region, the shielded gate field effect transistor further comprising:

an interconnect layer contacting the source and body regions; and

a dielectric material over the gate electrode for insulating the gate electrode and the interconnect layer from one another.

10. The shielded gate field effect transistor of claim 8 wherein the semiconductor region further includes a substrate of the first conductivity type, wherein the drift region extends over the substrate, and the trench extends through the body region and into the drift region.

11. The shielded gate field effect transistor of claim 8 wherein the semiconductor region further includes a substrate of the second conductivity type, wherein the drift region extends over the substrate, and the trench extends through the body region and into the drift region.

12. The shielded gate field effect transistor of claim 1 wherein the first dielectric layer comprises an oxide layer having a thickness within a range of 50-500 Å

.

13. The shielded gate field effect transistor of claim 1 wherein the second dielectric layer comprises a silicon nitride layer having a thickness within a range of 100-300 Å

.

14. The shielded gate field effect transistor of claim 1 wherein the inter-electrode dielectric comprises thermal oxide and has a thickness greater than a thickness of the gate dielectric.

15. The shielded gate field effect transistor of claim 1 wherein the shield dielectric further comprises a third dielectric layer, the second dielectric layer extending between the first and third dielectric layers.

16. The shielded gate field effect transistor of claim 15 wherein each of the first and third dielectric layers comprises an oxide layer and the second dielectric layer comprises a silicon nitride layer.

17. The shielded gate field effect transistor of claim 15 wherein the third dielectric layer has a thickness greater than a thickness of each of the first and second dielectric layers.

18. The shielded gate field effect transistor of claim 15 wherein the third dielectric layer comprises an oxide layer having a thickness within a range of 500-5,000 Å

.

19. A shielded gate field effect transistor, comprising:

a semiconductor region comprising a drift region of a first conductivity type and a body region of a second conductivity type extending over the drift region;

a trench extending through the body region and into the drift region;

source regions of the first conductivity type in the body region adjacent the trench;

a first oxide layer lining the upper and lower trench sidewalls and a bottom surface of the trench;

a silicon nitride layer extending over the first oxide layer along the upper and lower trench sidewalls and the bottom surface of the trench;

a second oxide layer extending over the silicon nitride layer along lower trench sidewalls and a bottom surface of the trench;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the drift region by the first oxide layer, the silicon nitride layer and the second oxide layer;

an inter-electrode dielectric overlying the shield electrode; and

a gate electrode in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the body region by the first oxide layer and the silicon nitride layer.

20. The shielded gate field effect transistor of claim 19 wherein the semiconductor region further includes a substrate of the first conductivity type, and the drift region extends over the substrate.

21. The shielded gate field effect transistor of claim 19 wherein the semiconductor region further includes a substrate of the second conductivity type, and the drift region extends over the substrate.

22. The shielded gate field effect transistor of claim 19 wherein the inter-electrode dielectric comprises thermal oxide and has a thickness greater that the combined thicknesses of the first oxide layer and the silicon nitride layer.

23. The shielded gate field effect transistor of claim 19 wherein the second oxide layer has a thickness greater than a thickness of each of the first oxide layer and the silicon nitride layer.

24. The shielded gate field effect transistor of claim 19 wherein the first oxide layer has a thickness within a range of 50-500 Å

, the silicon nitride layer has a thickness within a range of 100-300 Å

, and the second oxide layer has a thickness within a range of 500-5,000 Å

.

25. A method for forming a shielded gate field effect transistor, the method comprising:

forming a trench in a semiconductor region;

forming first, second and third dielectric layers extending along trench sidewalls and a bottom surface of the trench, the second dielectric layer being formed after the first dielectric layer and the third dielectric layer being formed after the second dielectric layer;

forming a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by the first, second and third dielectric layers;

removing portions of the third dielectric layer extending along upper trench sidewalls thereby exposing corresponding portions of the second shield dielectric layer;

forming an inter-electrode dielectric in the trench; and

forming a gate electrode in the trench over the inter-electrode dielectric.

26. The method of claim 25 wherein each of the first and third dielectric layers comprises an oxide layer and the second dielectric layer comprises a silicon nitride layer.

27-45. -45. (canceled)

46. A method for forming a shielded gate field effect transistor, the method comprising:

forming a trench in a semiconductor region;

forming a first oxide layer, a silicon nitride layer, and a second oxide layer extending along trench sidewalls and a bottom surface of the trench, the silicon nitride layer being formed after the first oxide layer and the second oxide layer being formed after the silicon nitride layer;

forming a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by the first oxide layer, the silicon nitride layer, and the second oxide layer;

removing portions of the second oxide layer extending along upper trench sidewalls thereby exposing corresponding portions of the silicon nitride layer;

forming an inter-electrode dielectric comprising thermal oxide in the trench; and

forming a gate electrode in the trench over the inter-electrode dielectric.

47. The method of claim 46 wherein the inter-electrode dielectric has a thickness greater than a combined thicknesses of the first oxide layer and silicon nitride layer.

48-59. -59. (canceled)

60. A method for forming a shielded gate field effect transistor, the method comprising:

forming a trench in a semiconductor region;

forming first and second dielectric layers extending along sidewalls and a bottom surface of the trench, the second dielectric layer being formed after the first dielectric layer;

forming a shield electrode in a lower portion of the trench;

forming an inter-electrode dielectric in the trench;

oxidizing the shield electrode to form an inter-electrode dielectric, the second dielectric layer comprising a material which inhibits oxide growth along upper trench sidewalls during oxidizing the shield electrode;

removing portions of the first and second dielectric layers extending along upper trench sidewalls to expose corresponding portions of upper trench sidewalls;

forming a gate dielectric lining the exposed upper trench sidewalls; and

forming a gate electrode in the trench over the inter-electrode dielectric.

61. The method of claim 60 wherein the first dielectric layer comprises an oxide layer and the second dielectric layer comprises a silicon nitride layer.

62-64. -64. (canceled)