Electronic device wafer level scale packges and fabrication methods thereof

• US 20090050995A1
• Filed: 11/28/2007
• Published: 02/26/2009
• Est. Priority Date: 08/24/2007
• Status: Abandoned Application

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: Liu, Chien-Hung, Lee, Sih-Dian
• Application Number:
  US11/987,227
• Publication Number:
  US 20090050995A1
• Time in Patent Office: Days
• US Class Current: 257/434
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A trench is formed by etching the semiconductor exposing an inter-layered dielectric (ILD) layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the trench is removed, and the ILD layer is subsequently removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an L-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Claims

1. A fabrication method for an electronic device chip scale package, comprising:

providing a semiconductor wafer with a plurality of electronic devices thereon;

bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer;

etching the back of the semiconductor wafer to create a trench;

conformably depositing an insulating layer on the back of the semiconductor wafer;

removing the insulator layer at the bottom of the trench, exposing part of a pair of contact pads;

conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an L-shaped connection constructed by the conductive layer and the contact pad; and

forming exterior connections and terminal contact pads connecting the L-shaped connection.

2. The fabrication method as claimed in claim 1, wherein the plurality of electronic devices comprise an integrated circuit device, an optoelectronic device, an electromechanical device, or a surface acoustic wave (SAW) device.

3. The fabrication method as claimed in claim 2, wherein the optoelectronic device comprises a CMOS image sensing device.

4. The fabrication method as claimed in claim 1, wherein the supporting substrate is transparent comprising lens quality glass or quartz.

5. The fabrication method as claimed in claim 1, wherein deposition techniques of the insulating layer comprises spray coating, sputtering, printing, application and spin coating.

6. The fabrication method as claimed in claim 1, wherein the insulating layer comprises epoxy, polyimide, resin, silicon oxide, metal oxide, or silicon nitride.

7. The fabrication method as claimed in claim 1, wherein after deposition of the insulating layer, further comprising:

forming a patterned mask layer on the insulating layer exposing the insulating layer at the bottom of the trench; and

etching the exposed insulating layer at the bottom of the trench using the patterned mask layer.

8. The fabrication method as claimed in claim 1, wherein the exposed part of a pair of contact pads comprises a vertical portion and a horizontal portion.

9. The fabrication method as claimed in claim 1, further comprises cutting the semiconductor wafer and the supporting substrate to divide each electronic device chip scale package.

10. A wafer level package of electronic devices, comprising:

a semiconductor wafer with a plurality of electronic devices thereon bonded with a supporting substrate, wherein each electronic device comprises a pair of contact pads and an inter-layered dielectric (ILD) covered thereon exposing a vertical portion and a horizontal portion; and

a conductive layer disposed on the exterior of the wafer level package of electronic devices and conformably contacting the exposed vertical and horizontal portions of the pair of contact pads, thereby constructing an L-shaped connection;

wherein the L-shaped connection extends to a plurality of contact terminals on the back of the wafer level package of electronic devices.

11. The wafer level package of electronic devices as claimed in claim 10, wherein the plurality of electronic devices comprise an integrated circuit device, an optoelectronic device, an electromechanical device, or a surface acoustic wave (SAW) device.

12. The wafer level package of electronic devices as claimed in claim 11, wherein the optoelectronic device comprises a CMOS image sensing device.

13. The wafer level package of electronic devices as claimed in claim 10, wherein the supporting substrate is transparent comprising lens quality glass or quartz.

14. The wafer level package of electronic devices as claimed in claim 10, further comprising an insulating layer on the back of the semiconductor wafer, wherein the conductive layer is conformably formed on the insulating layer, the inter-layer dielectric (ILD), and the pair of contact pads.

15. The wafer level package of electronic devices as claimed in claim 14, wherein the insulating layer comprises epoxy, polyimide, resin, silicon oxide, metal oxide, or silicon nitride.

16. The wafer level package of electronic devices as claimed in claim 14, wherein the isolation structure exposes a vertical portion and a horizontal portion of the inter-layer dielectric (ILD), and the conductive layer conformably contacts the exposed vertical and horizontal portions of the inter-layer dielectric (ILD).

17. A wafer level package of electronic devices, comprising:

a semiconductor wafer with a plurality of CMOS image sensing devices thereon bonded with a supporting substrate, wherein each CMOS image sensing device comprises a pair of contact pads and an inter-layered dielectric (ILD);

an insulating layer conformably disposed on the back of the semiconductor wafer exposing a first vertical portion and a first horizontal portion of the pair of contact pads and a second vertical portion and a second horizontal portion of the inter-layered dielectric (ILD); and

a conductive layer disposed on the exterior of the wafer level package of electronic devices and conformably contacts the exposed first vertical and first horizontal portions of the pair of contact pads and the exposed first vertical and first horizontal portions of the inter-layered dielectric (ILD), thereby constructing an L-shaped connection;

wherein the L-shaped connection extends to a plurality of contact terminals on the back of the wafer level package of electronic devices.

18. The wafer level package of electronic devices as claimed in claim 17, wherein the supporting substrate is transparent comprising lens quality glass or quartz.

19. The wafer level package of electronic devices as claimed in claim 17, wherein the isolating layer comprises epoxy, polyimide, resin, silicon oxide, metal oxide, or silicon nitride.