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Electronic device wafer level scale packages and fabrication methods thereof

  • US 20090050996A1
  • Filed: 11/28/2007
  • Published: 02/26/2009
  • Est. Priority Date: 08/24/2007
  • Status: Active Grant
First Claim
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1. A fabrication method for an electronic device chip scale package, comprising:

  • providing a semiconductor wafer with a plurality of electronic devices thereon;

    bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer;

    etching the back of the semiconductor wafer to create a first trench;

    conformably depositing an insulating layer on the back of the semiconductor wafer;

    etching the insulator layer at the bottom of the first trench to create a second trench;

    sequentially removing the insulating layer and a portion of the inter-layered dielectric (ILD) layer to expose part of a pair of contact pads;

    conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an S-shaped connection constructed by the conductive layer and the contact pads; and

    forming exterior connections and terminal contact pads connecting the S-shaped connection.

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