Electronic device wafer level scale packages and fabrication methods thereof
First Claim
1. A fabrication method for an electronic device chip scale package, comprising:
- providing a semiconductor wafer with a plurality of electronic devices thereon;
bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer;
etching the back of the semiconductor wafer to create a first trench;
conformably depositing an insulating layer on the back of the semiconductor wafer;
etching the insulator layer at the bottom of the first trench to create a second trench;
sequentially removing the insulating layer and a portion of the inter-layered dielectric (ILD) layer to expose part of a pair of contact pads;
conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an S-shaped connection constructed by the conductive layer and the contact pads; and
forming exterior connections and terminal contact pads connecting the S-shaped connection.
1 Assignment
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Accused Products
Abstract
Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.
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Citations
15 Claims
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1. A fabrication method for an electronic device chip scale package, comprising:
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providing a semiconductor wafer with a plurality of electronic devices thereon; bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer; etching the back of the semiconductor wafer to create a first trench; conformably depositing an insulating layer on the back of the semiconductor wafer; etching the insulator layer at the bottom of the first trench to create a second trench; sequentially removing the insulating layer and a portion of the inter-layered dielectric (ILD) layer to expose part of a pair of contact pads; conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an S-shaped connection constructed by the conductive layer and the contact pads; and forming exterior connections and terminal contact pads connecting the S-shaped connection. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A wafer level package of electronic devices, comprising:
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a semiconductor wafer with a plurality of electronic devices thereon bonded with a supporting substrate, wherein each electronic device comprises a pair of contact pads and an inter-layered dielectric (ILD) covered thereon exposing a vertical portion and a horizontal portion; and a conductive layer disposed on the exterior of the wafer level package of electronic devices and conformably contacting the exposed vertical and horizontal portions of the pair of contact pads, thereby constructing an S-shaped connection; wherein the S-shaped connection extends to a plurality of contact terminals on the back of the wafer level package of electronic devices. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification