SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

• US 20090051018A1
• Filed: 08/21/2007
• Published: 02/26/2009
• Est. Priority Date: 08/21/2007
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Moline, Daniel D.
• Granted Patent: US 8,067,834 B2
• Time in Patent Office: Days
• US Class Current: 257/675
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/81205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 23/047 the other leads being parallel to the base
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/36 Structure, shape, material or disposition of the strap connectors prior to the connecting process
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed.

Claims

1. A semiconductor component, comprising:

a heat sink having a first surface, a second surface that is parallel to, or substantially parallel to, the first surface of the heat sink, and a cavity extending from the first surface of the heat sink into the heat sink;

a semiconductor die having a first surface and a second surface that is parallel to, or substantially parallel to, the first surface of the semiconductor die, wherein the semiconductor die comprises a first terminal adjacent to the first surface of the semiconductor die, a second terminal adjacent to the first surface of the semiconductor die, and a third terminal adjacent to the second surface of the semiconductor die, and wherein the first terminal is electrically isolated from the second terminal and the third terminal and the second terminal is electrically isolated from the third terminal, wherein at least a portion of the semiconductor die is in the cavity and the second terminal is coupled to the heat sink;

a leadframe structure coupled to the first terminal of the semiconductor die; and

a dielectric material in at least a portion of the cavity, wherein the dielectric material surrounds a first portion of the leadframe structure and a first portion of the semiconductor die.

2. The semiconductor component of claim 1, wherein the dielectric material is a glob top material or a mold compound.

3. The semiconductor component of claim 1,

wherein the heat sink further comprises a pedestal portion in the cavity and extending from a lower portion of the cavity;

wherein the pedestal portion has a first surface that is noncoplanar to the first and second surfaces of the heat sink and is parallel to, or substantially parallel to, the first and second surfaces of the heat sink;

wherein the first surface extends from the lower portion of the cavity to a height that is below the first surface of the heat sink; and

wherein the second terminal is coupled to the first surface of the pedestal portion of the heat sink.

4. The semiconductor component of claim 1, further comprising:

a first lead coupled to a second portion of the leadframe structure; and

a second lead coupled to the third terminal of the semiconductor die.

5. The semiconductor component of claim 4,

wherein the first lead is electrically isolated from the second lead;

wherein the first lead has a first surface that is coplanar to, or substantially coplanar to, a first surface of the second lead and is noncoplanar to the first and second surfaces of the heat sink;

wherein the semiconductor die is a discrete transistor; and

wherein the first terminal is a gate terminal, the second terminal is a source terminal, and the third terminal is a drain terminal.

6. The semiconductor component of claim 1, wherein a depth of the cavity of the heat sink is greater than a thickness of the semiconductor die and wherein the leadframe structure has at least one opening.

7. A method to manufacture a semiconductor component, wherein the semiconductor component comprises a heat sink and a semiconductor die having a first surface and a second surface that is parallel to, or substantially parallel to, the first surface, wherein the semiconductor die comprises a first terminal adjacent to the first surface, a second terminal adjacent to the first surface, and a third terminal adjacent to the second surface, and wherein the first terminal is electrically isolated from the second terminal and the third terminal and the second terminal is electrically isolated from the third terminal, the method comprising:

attaching a first portion of a leadframe structure to the first terminal of the semiconductor die; and

attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink.

8. The method of claim 7, wherein the heat sink has a first surface and a second surface that is parallel to, or substantially parallel to, the first surface of the heat sink and has a projection portion extending from the first surface of the heat sink, wherein the projection portion has a first surface that is noncoplanar to the first surface of the heat sink and parallel to, or substantially parallel to, the first surface of the heat sink, and wherein attaching the second terminal comprises attaching the second terminal to the first surface of the projection portion of the heat sink.

9. The method of claim 8, wherein the leadframe structure has at least one opening, a first rail portion, a second rail portion coupled to the first rail portion and separated from the first rail portion by the at least one opening, and comprises copper, gold, silver, tantalum, or tungsten, wherein the second rail portion is parallel to, or substantially parallel to, the first rail portion, wherein the attaching of the first portion of the leadframe structure comprises attaching the first rail portion of the leadframe structure to the first terminal of the semiconductor die, and the method further comprising coupling the second rail portion to a first lead of the semiconductor component, and coupling the third terminal of the semiconductor die to a second lead of the semiconductor component, wherein the first lead is electrically isolated from the second lead.

10. The method of claim 9, wherein the semiconductor die is a discrete transistor, wherein the first terminal is a gate terminal, the second terminal is a source terminal, and the third terminal is a drain terminal, and wherein the first lead has a first surface that is coplanar to, or substantially coplanar to, a first surface of the second lead and is noncoplanar to the first surface of the heat sink and the second surface of the heat sink.

11. The method of claim 7,

wherein the heat sink comprises a first surface, a second surface, and a third surface that is parallel to, or substantially parallel to, the first and second surfaces of the heat sink;

wherein the heat sink further comprises a cavity extending from the first surface of the heat sink into the heat sink;

wherein the second surface of the heat sink forms a lower boundary of the cavity;

wherein the heat sink further comprises a projection portion extending from the second surface of the heat sink;

wherein the projection portion has a first surface that is noncoplanar to the first, second, and third surfaces of the heat sink and is parallel to, or substantially parallel to, the first and second surfaces of the heat sink; and

wherein the attaching of the second terminal comprises attaching the second terminal of the semiconductor die to the first surface of the projection portion of the heat sink.

12. The method of claim 11, further comprising:

forming a glob top material in the cavity to surround a portion of the semiconductor die and the first portion of the leadframe structure, wherein the forming of the glob top material is after the attaching of the second terminal to the first surface of the projection portion and wherein the third terminal of the semiconductor die is exposed after the forming of the glop top material in the cavity and a second portion of the leadframe structure is exposed after the forming of the glop top material in the cavity.

13. A semiconductor component, comprising:

a heat spreader having a first surface and a cavity extending inward from the first surface;

a semiconductor die, wherein a first portion of the semiconductor die is over the first surface and a second portion of the semiconductor die is over the cavity; and

an interposer, wherein at least a portion of the interposer is in the cavity and wherein the interposer comprises a flexible dielectric material.

14. The semiconductor component of claim 13, wherein the semiconductor die has a top surface and a bottom surface that is parallel to, or substantially parallel to, the top surface of the semiconductor die, the semiconductor die has a first terminal on the top surface of the semiconductor die and coupled to the interposer, a second terminal on the top surface of the semiconductor die and coupled to the first surface of the heat spreader, and a third terminal on the bottom surface of the semiconductor die, wherein the first terminal, the second terminal, and the third terminal are electrically isolated from each other.

15. The semiconductor component of claim 13, wherein the semiconductor die is a discrete transistor and wherein the first terminal is a gate terminal, the second terminal is a source terminal, and the third terminal is a drain terminal.

16. The semiconductor component of claim 15, wherein the semiconductor component is a discrete component having a gate lead coupled to the gate terminal, a source lead coupled to the source terminal, and a drain lead coupled to the drain terminal, wherein a first surface of the gate lead is coplanar to, or substantially coplanar to, a first surface of the source lead, and wherein the first surface of the source lead is coplanar to, or substantially coplanar to, a first surface of the drain lead.

17. The semiconductor component of claim 13, wherein the dielectric material comprises polyimide.

18. A semiconductor component, comprising:

a heat spreader having a first surface and a cavity extending inward from the first surface;

a semiconductor die, wherein a first portion of the semiconductor die is over the first surface and a second portion of the semiconductor die is over the cavity; and

a polymer material in at least a portion of the cavity.

19. The semiconductor component of claim 18, further comprising an interposer, wherein at least a portion of the interposer is in the cavity below a plane that is coplanar to, or substantially coplanar to, the first surface of the heat spreader.

20. The semiconductor component of claim 19, wherein a depth of the cavity is greater than a thickness of the interposer.

21. A semiconductor component, comprising:

a heat spreader having a first surface and a cavity extending inward from the first surface;

a semiconductor die, wherein a first portion of the semiconductor die is over the first surface and a second portion of the semiconductor die is over the cavity; and

an interposer, wherein at least a portion of the interposer is in the cavity and wherein the interposer comprises;

a dielectric material having a top surface and a bottom surface that is parallel to, or substantially parallel to, the top surface of the dielectric material; and

a plurality of conductive strips over the top surface of the dielectric material.

22. The semiconductor component of claim 21, wherein a first conductive strip of the plurality of conductive strips has a surface that is coplanar to, or substantially coplanar to, the first surface of the heat spreader.

23. The semiconductor component of claim 21, wherein the semiconductor die has a top surface and a bottom surface that is parallel to, or substantially parallel to, the top surface of the semiconductor die, the semiconductor die has a first terminal on the top surface of the semiconductor die and contacting the first conductive strip of the plurality of conductive strips, a second terminal on the top surface of the semiconductor die and contacting the first surface of the heat spreader, and a third terminal on the bottom surface of the semiconductor die, wherein the first terminal, the second terminal, and the third terminal are electrically isolated from each other.

24. The semiconductor component of claim 21, wherein the dielectric material comprises a ceramic, a polyimide, or a polymer material.