THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE

• US 20090051039A1
• Filed: 08/24/2007
• Published: 02/26/2009
• Est. Priority Date: 08/24/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kai-Ming, Kuo, Chen-Cheng, Chen-Shien, Chen, Chen, Chih-Hua
• Granted Patent: US 7,973,413 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via.

Claims

1. A semiconductor device, comprising:

a substrate having a front surface and a back surface;

an interconnect structure formed on the front surface of the substrate, and wherein the interconnect structure has a first surface opposite the front surface of the substrate, and wherein the interconnect structure includes a first conductive layer, a second conductive layer overlying the first conductive layer, and an isolation layer interposing the first conductive layer and the second conductive layer; and

a tapered profile via extending from the first surface of the interconnect structure to the back surface of the substrate.

2. The device of claim 1, wherein the tapered profile via includes conductive material.

3. The device of claim 1, further comprising a hard mask layer formed on the interconnect structure.

4. The device of claim 3, wherein the hard mask layer includes a material selected from the group consisting of an oxide, a nitride, and a carbide.

5. The device of claim 3, wherein the hard mask layer includes a thickness of approximately 0.2 μ

m.

6. The device of claim 1, wherein the tapered profile via includes a first width at the first surface of the interconnect structure and a second width at the back surface of the substrate, and wherein the second width is less than the first width.

7. The device of claim 1, wherein sidewalls of the tapered profile via are directly adjacent a plurality of insulating layers.

8. The device of claim 1, wherein the substrate includes at least one device feature formed on the front surface.

9. The device of claim 1, further comprising:

an insulating layer formed on the interconnect structure, wherein the insulating layer includes an opening, and wherein the opening includes conductive material contacting the tapered profile via.

10. The device of claim 9, wherein the insulating layer includes an oxide material.

11. The device of claim 9, wherein the insulating layer is approximately 10 μ

m in thickness.

12. The device of claim 1, further comprising an insulating layer formed on the substrate, wherein the insulating layer is etched back from a region overlying the tapered profile via.

13. A device, comprising:

a substrate having a front surface and a back surface;

a first interconnect structure formed on the front surface and having a first surface opposite the front surface of the substrate, wherein the interconnect structure includes a first metal layer and a second metal layer interposed by a dielectric layer, and wherein a conductive via connects the first metal layer and the second metal layer;

an insulating layer formed on the first surface of the interconnect structure, wherein the insulating layer includes an aperture; and

a second interconnect structure, electrically coupled to the first interconnect structure, and formed on the substrate comprising the aperture in the insulating layer and a tapered profile via extending from the aperture in the insulating layer to the back surface of the substrate, wherein the aperture and the tapered profile via include conductive material.

14. The device of claim 13, wherein the insulating layer includes silicon oxide.

15. The device of claim 13, wherein the aperture in the insulating layer includes a first width and the tapered profile via includes a second width, wherein the first width is greater than the second width.

16. The device of claim 13, wherein the second interconnect structure comprises a conductive material selected from the group consisting of:

copper, aluminum, tungsten, tantalum, titanium, nickel, cobalt, metal silicide, metal nitride, polysilicon, gold, silver and/or combinations thereof.

17. A device, comprising:

a substrate having a device feature and an interconnect structure electrically coupled to the device feature;

wherein the substrate includes a top surface and a back surface opposing the top surface, wherein the interconnect structure lies below the top surface, and wherein the interconnect structure includes conductive lines electrically coupled by conductive vias;

an insulating layer formed on the top surface of the substrate having an opening of a first width, wherein the opening of the first width is filled with conductive material;

a tapered profile via extending from the top surface of the substrate to the back surface of the substrate, wherein the tapered profile via has a second width at the top surface of the substrate and a third width at the back surface of the substrate, and wherein the first width is greater than the second width, and the second width is greater than the third width.

18. The device of claim 17, wherein first width is approximately 130 μ

m, the second width is approximately 30 μ

m, and the third width is approximately 20 μ

m.

19. The device of claim 17,

further comprising a hard mask layer formed on the top surface of the substrate and underlying the insulating layer.

20. The device of claim 19, where the hard mask layer includes an opening having approximately the second width.