NON-VOLATILE SHADOW LATCH USING A NANOTUBE SWITCH

• US 20090052246A1
• Filed: 06/30/2008
• Published: 02/26/2009
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: HUANG, X. M., SIVARAJAN, Ramesh, RUECKES, Thomas, BERTIN, Claude L., STRASBURG, Max, KONSEK, Steven L., MEINHOLD, Mitchell, GUO, Frank
• Granted Patent: US 7,986,546 B2
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.

Claims

1. A non-volatile memory cell comprising:

a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and

a shadow memory device coupled to the volatile storage device so as to receive and store the corresponding logic state, said shadow memory device including a non-volatile two-terminal nanotube switch, the two-terminal nanotube switch comprising first and second terminals and a nanotube article, the two-terminal nanotube switch storing the corresponding logic state of the shadow memory device in response to electrical stimulus applied only to at least one of the first and second terminals;

wherein the non-volatile memory cell has a normal mode of operation and a low power retention mode of operation;

wherein during the normal mode of operation the volatile storage device operates under nominal voltage;

wherein during the lower power retention mode of operation the shadow memory device holds the corresponding logic state of the volatile storage device even when the volatile storage device operates under lower-than-nominal voltage.

2. The non-volatile memory cell of claim 1, wherein during the low power retention mode of operation the volatile storage device is powered down.

3. The non-volatile memory cell of claim 1, wherein during the low power retention mode of operation the volatile storage device and the shadow memory device are powered down.

4. The non-volatile memory cell of claim 1, wherein the shadow memory device has a plurality of logic states characterized by the resistance of an electrical pathway across the first and second terminals.

5. The non-volatile memory cell of claim 4, wherein an off logic state stored by the shadow memory device is characterized by a high resistance of an electrical pathway across the first and second terminals.

6. The non-volatile memory cell of claim 4, wherein an off logic state is stored in the shadow memory device by applying significantly higher-than-nominal voltage across the first and second terminals.

7. The non-volatile memory cell of claim 4, wherein a logic low at the volatile storage device is stored as an off logic state at the shadow memory device.

8. The non-volatile memory cell of claim 4, wherein an on logic state stored by the shadow memory device is characterized by a low resistance of an electrical pathway across the first and second terminals.

9. The non-volatile memory cell of claim 4, wherein an on logic state is stored in the shadow memory device by applying higher-than-nominal voltage across the first and second terminals.

10. The non-volatile memory cell of claim 4, wherein a logic high at the volatile storage device is stored as an on logic state at the non-volatile two-terminal nanotube.

11. A non-volatile memory cell comprising:

a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and

a shadow memory device coupled to the volatile storage device so as to receive and store the corresponding logic state, said shadow memory device including a single non-volatile two-terminal nanotube switch, the single two-terminal nanotube switch comprising first and second terminals and a nanotube article, the single two-terminal nanotube switch storing the corresponding logic state of the shadow memory device in response to electrical stimulus applied only to at least one of the first and second terminals;

wherein the non-volatile memory cell has a normal mode of operation and a low power retention mode of operation;

wherein during the normal mode of operation the volatile storage device operates under nominal voltage;

wherein during the lower power retention mode of operation the shadow memory device holds the corresponding logic state of the volatile storage device even when the volatile storage device operates under lower-than-nominal voltage.

12. The non-volatile memory cell of claim 11, wherein during the low power retention mode of operation the volatile storage device is powered down.

13. The non-volatile memory cell of claim 11, wherein during the low power retention mode of operation the volatile storage device and the shadow memory device are powered down.

14. The non-volatile memory cell of claim 11, wherein the shadow memory device has a plurality of logic states characterized by the resistance of an electrical pathway across the first and second terminals.

15. The non-volatile memory cell of claim 14, wherein an off logic state stored by the shadow memory device is characterized by a high resistance of an electrical pathway across the first and second terminals.

16. The non-volatile memory cell of claim 14, wherein an off logic state is stored in the shadow memory device by applying significantly higher-than-nominal voltage across the first and second terminals.

17. The non-volatile memory cell of claim 14, wherein a logic low at the volatile storage device is stored as an off logic state at the shadow memory device.

18. The non-volatile memory cell of claim 14, wherein an on logic state stored by the shadow memory device is characterized by a low resistance of an electrical pathway across the first and second terminals.

19. The non-volatile memory cell of claim 14, wherein an on logic state is stored in the shadow memory device by applying higher-than-nominal voltage across the first and second terminals.

20. The non-volatile memory cell of claim 14, wherein a logic high at the volatile storage device is stored as an on logic state at the non-volatile two-terminal nanotube.