PROGRAM AND ERASE METHODS FOR NONVOLATILE MEMORY
First Claim
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1. A method of programming a nonvolatile memory device having a charge storage layer, comprising:
- performing at least one unit programming loop, each unit programming loop including,applying at least two programming pulses to a wordline,applying at least two time delays to the wordline, andapplying a verifying pulse to the wordline.
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Abstract
Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying at least one programming pulse, at least one erasing pulse, at least one time delay, at least one soft erase pulse, at least one soft programming pulse and/or at least one verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.
32 Citations
47 Claims
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1. A method of programming a nonvolatile memory device having a charge storage layer, comprising:
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performing at least one unit programming loop, each unit programming loop including, applying at least two programming pulses to a wordline, applying at least two time delays to the wordline, and applying a verifying pulse to the wordline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A nonvolatile memory device, comprising:
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an array of memory cell transistors connected by a plurality of word lines and a plurality of bit lines; and programming logic, performing at least one unit programming loop, wherein for each unit programming loop, the programming logic applies at least two programming pulses to a selected one of the plurality of word lines and a pass pulse to unselected ones of the plurality of word lines, applies at least two time delays to the selected one of the plurality of word lines and applies a verifying pulse to the selected one of the plurality of word lines and a read pulse to unselected ones of the plurality of word lines.
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20. A system, comprising:
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a memory including an array of memory cell transistors connected by a plurality of word lines and a plurality of bit lines, and programming logic performing at least one unit programming loop, wherein for each unit programming loop, the programming logic applies at least two programming pulses to a selected one of the plurality of word lines and a pass pulse to unselected ones of the plurality of word lines, applies at least two time delays to the selected one of the plurality of word lines and applies a verifying pulse to the selected one of the plurality of word lines and a read pulse to unselected ones of the plurality of word lines; and a memory controller, for controlling the memory.
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21. A system, comprising:
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a memory including an array of memory cell transistors connected by a plurality of word lines and a plurality of bit lines, and programming logic performing at least one unit programming loop, wherein for each unit programming loop, the programming logic applies at least two programming pulses to a selected one of the plurality of word lines and a pass pulse to unselected ones of the plurality of word lines, applies at least two time delays to the selected one of the plurality of word lines and applies a verifying pulse to the selected one of the plurality of word lines and a read pulse to unselected ones of the plurality of word lines; and a controller, for controlling the memory; a user interface for enabling access to the memory; a modem permitting information in the memory to be transmitted; a battery for supplying power to the memory; and a bus for connecting the memory, the controller, the user interface, the modem and the battery.
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22. A method of erasing a nonvolatile memory device having a charge storage layer, comprising:
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performing at least one unit erasing loop, each unit erasing loop including, applying at least two erasing pulses to a wordline, applying at least two time delays to the wordline, and applying a verifying pulse to the wordline. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 47, 38, 39, 40, 41, 42)
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43. A nonvolatile memory device, comprising:
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an array of memory cell transistors connected by a plurality of word lines and a plurality of bit lines; and programming logic, including an X-decoder, performing at least one unit erasing loop, wherein for each unit erasing loop, the X-decoder applies at least two erasing pulses to a substrate of the nonvolatile memory device, applies at least two time delays, and applies a verifying pulse to plurality of word lines.
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44. A system, comprising:
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a memory including an array of memory cell transistors connected by a plurality of word lines and a plurality of bit lines and erasing logic performing at least one unit erasing loop, wherein for each unit erasing loop, the erasing logic applies at least two erasing pulses to a substrate of the nonvolatile memory device, applies at least two time delays, and applies a verifying pulse to plurality of word lines; and a memory controller, for controlling the memory.
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45. A system, comprising:
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a memory including an array of memory cell transistors connected by a plurality of word lines and a plurality of bit lines and erasing logic performing at least one unit erasing loop, wherein for each unit erasing loop, the erasing logic applies at least two erasing pulses to a substrate of the nonvolatile memory device, applies at least two time delays, and applies a verifying pulse to plurality of word lines; and a controller, for controlling the memory; a user interface for enabling access to the memory; a modem permitting information in the memory to be transmitted; a battery for supplying power to the memory; and a bus for connecting the memory, the controller, the user interface, the modem and the battery.
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Specification