SEMICONDUCTOR DEVICE COMPRISING LIGHT-EMITTING ELEMENT AND LIGHT-RECEIVING ELEMENT, AND MANUFACTURING METHOD THEREFOR

• US 20090053856A1
• Filed: 10/30/2008
• Published: 02/26/2009
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Ohsumi, Takashi
• Granted Patent: US 8,211,750 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/02325 : the optical elements not being integrated nor being directly associated with the device

Abstract

A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes a cut surface formed by dicing and constituted by only the substrate and the sealant. Since the cut surface has a single-layer structure as a result of forming the sealant in a single step, moisture cannot infiltrate through the sealant, hence a device resistant to corrosion and operational defects is provided.

Claims

1. A manufacturing method for a semiconductor device, comprising:

preparing a substrate having a first face and a second face opposing said first face, for transmitting light through said first face and said second face;

providing a wiring layer having a first region and a second region adjacent to said first region on said first face of said substrate;

providing a bump electrode on said first region of said wiring layer;

providing a semiconductor chip having a third face such that said third face is connected to said bump electrode;

providing a columnar electrode having a fourth face and a fifth face opposing said fourth face such that said fourth face contacts said second region of said wiring layer;

providing a first sealant covering said first face of said substrate such that said fifth face of said columnar electrode is exposed;

providing an external connection terminal on said fifth face of said columnar electrode; and

dividing said substrate and said first sealant into individual semiconductor devices through dicing.

2. The manufacturing method for a semiconductor device according to claim 1, wherein said second face of said substrate comprises a third region and a fourth region surrounding said third region, and

said manufacturing method comprises:

providing a second sealant covering said fourth region, said substrate, and a side face of said first sealant; and

providing a lens, an outside edge portion of which is fixed to said second sealant provided on said fourth region.

3. The manufacturing method for a semiconductor device according to claim 1, wherein said second face of said substrate comprises a third region and a fourth region surrounding said third region, and

said manufacturing method comprises:

removing said third region and said fourth region of said second face such that said third region protrudes in a direction which increases the distance between said first face and said second face.

4. A manufacturing method for a semiconductor device, comprising:

preparing a substrate having a first face comprising a first region, a second region surrounding said first region, and a third region surrounding said second region, and a second face opposing said first face, for transmitting light through said first face and said second face;

providing a first wiring layer on said first region of said substrate;

providing second and third wiring layers extending over said second region and said third region of said substrate;

providing first and second bump electrodes on said first wiring layer;

providing a third bump electrode on said second wiring layer provided on said second region of said substrate;

providing a fourth bump electrode on said third wiring layer provided on said second region of said substrate;

providing a first semiconductor chip on said first and third bump electrodes;

providing a second semiconductor chip on said second and fourth bump electrodes;

providing a first columnar electrode on said second wiring layer provided on said third region of said substrate;

providing a second columnar electrode on said third wiring layer provided on said third region of said substrate;

providing a sealant covering said first face of said substrate, excluding a tip end of said first columnar electrode and a tip end of said second columnar electrode;

providing a first external connection terminal on said exposed tip end of said first columnar electrode;

providing a second external connection terminal on said exposed tip end of said second columnar electrode; and

dividing said substrate and said sealant into individual semiconductor elements through dicing.

5. A manufacturing method for a semiconductor device, comprising:

preparing a substrate having a first face comprising a first region formed with a first semiconductor element, a second region formed with a second semiconductor element, and a third region surrounding said first region and said second region, and a second face opposing said first face, for transmitting light through said first face and said second face;

providing a first wiring layer having one end and another end such that said one end is disposed on said first region of said substrate and said another end is disposed on said second region of said substrate;

providing a second wiring layer having one end and another end such that said one end is disposed on said first region of said substrate and said another end is disposed on said third region of said substrate;

providing a third wiring layer having one end and another end such that said one end is disposed on said second region of said substrate and said another end is disposed on said third region of said substrate;

providing a first columnar electrode on said second wiring layer provided on said third region of said substrate;

providing a second columnar electrode on said third wiring layer provided on said third region of said substrate;

providing a sealant covering said first face of said substrate such that a tip end of said first columnar electrode and a tip end of said second columnar electrode are exposed;

providing a first external connection terminal on said exposed tip end of said first columnar electrode;

providing a second external connection terminal on said exposed tip end of said second columnar electrode; and

dividing said substrate and said sealant into individual semiconductor devices through dicing.